static_inst.hh (7692:8173327c9c65) | static_inst.hh (7720:65d338a8dba4) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 141 unchanged lines hidden (view full) --- 150 151 152 void printDataInst(std::ostream &os, bool withImm) const; 153 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 154 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 155 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 156 uint32_t imm) const; 157 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 141 unchanged lines hidden (view full) --- 150 151 152 void printDataInst(std::ostream &os, bool withImm) const; 153 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 154 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 155 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 156 uint32_t imm) const; 157 |
158 void 159 advancePC(PCState &pcState) const 160 { 161 pcState.advance(); 162 } 163 |
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158 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 159 160 static inline uint32_t 161 cpsrWriteByInstr(CPSR cpsr, uint32_t val, 162 uint8_t byteMask, bool affectState, bool nmfi) 163 { 164 bool privileged = (cpsr.mode != MODE_USER); 165 --- 48 unchanged lines hidden (view full) --- 214 215 return ((spsr & ~bitMask) | (val & bitMask)); 216 } 217 218 template<class XC> 219 static inline Addr 220 readPC(XC *xc) 221 { | 164 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 165 166 static inline uint32_t 167 cpsrWriteByInstr(CPSR cpsr, uint32_t val, 168 uint8_t byteMask, bool affectState, bool nmfi) 169 { 170 bool privileged = (cpsr.mode != MODE_USER); 171 --- 48 unchanged lines hidden (view full) --- 220 221 return ((spsr & ~bitMask) | (val & bitMask)); 222 } 223 224 template<class XC> 225 static inline Addr 226 readPC(XC *xc) 227 { |
222 Addr pc = xc->readPC(); 223 if (isThumb(pc)) 224 return pc + 4; 225 else 226 return pc + 8; | 228 return xc->pcState().instPC(); |
227 } 228 | 229 } 230 |
229 // Perform an regular branch. | |
230 template<class XC> 231 static inline void 232 setNextPC(XC *xc, Addr val) 233 { | 231 template<class XC> 232 static inline void 233 setNextPC(XC *xc, Addr val) 234 { |
234 Addr npc = xc->readNextPC(); 235 if (isThumb(npc)) { 236 val &= ~mask(1); 237 } else { 238 val &= ~mask(2); 239 } 240 xc->setNextPC((npc & PcModeMask) | 241 (val & ~PcModeMask)); | 235 PCState pc = xc->pcState(); 236 pc.instNPC(val); 237 xc->pcState(pc); |
242 } 243 244 template<class T> 245 static inline T 246 cSwap(T val, bool big) 247 { 248 if (big) { 249 return gtobe(val); --- 24 unchanged lines hidden (view full) --- 274 return gtoh(conv.tVal); 275 } 276 277 // Perform an interworking branch. 278 template<class XC> 279 static inline void 280 setIWNextPC(XC *xc, Addr val) 281 { | 238 } 239 240 template<class T> 241 static inline T 242 cSwap(T val, bool big) 243 { 244 if (big) { 245 return gtobe(val); --- 24 unchanged lines hidden (view full) --- 270 return gtoh(conv.tVal); 271 } 272 273 // Perform an interworking branch. 274 template<class XC> 275 static inline void 276 setIWNextPC(XC *xc, Addr val) 277 { |
282 Addr stateBits = xc->readPC() & PcModeMask; 283 Addr jBit = PcJBit; 284 Addr tBit = PcTBit; 285 bool thumbEE = (stateBits == (tBit | jBit)); 286 287 Addr newPc = (val & ~PcModeMask); 288 if (thumbEE) { 289 if (bits(newPc, 0)) { 290 newPc = newPc & ~mask(1); 291 } else { 292 panic("Bad thumbEE interworking branch address %#x.\n", newPc); 293 } 294 } else { 295 if (bits(newPc, 0)) { 296 stateBits = tBit; 297 newPc = newPc & ~mask(1); 298 } else if (!bits(newPc, 1)) { 299 stateBits = 0; 300 } else { 301 warn("Bad interworking branch address %#x.\n", newPc); 302 } 303 } 304 newPc = newPc | stateBits; 305 xc->setNextPC(newPc); | 278 PCState pc = xc->pcState(); 279 pc.instIWNPC(val); 280 xc->pcState(pc); |
306 } 307 308 // Perform an interworking branch in ARM mode, a regular branch 309 // otherwise. 310 template<class XC> 311 static inline void 312 setAIWNextPC(XC *xc, Addr val) 313 { | 281 } 282 283 // Perform an interworking branch in ARM mode, a regular branch 284 // otherwise. 285 template<class XC> 286 static inline void 287 setAIWNextPC(XC *xc, Addr val) 288 { |
314 Addr stateBits = xc->readPC() & PcModeMask; 315 Addr jBit = PcJBit; 316 Addr tBit = PcTBit; 317 if (!jBit && !tBit) { 318 setIWNextPC(xc, val); 319 } else { 320 setNextPC(xc, val); 321 } | 289 PCState pc = xc->pcState(); 290 pc.instAIWNPC(val); 291 xc->pcState(pc); |
322 } 323 324 inline Fault 325 disabledFault() const 326 { 327#if FULL_SYSTEM 328 return new UndefinedInstruction(); 329#else 330 return new UndefinedInstruction(machInst, false, mnemonic, true); 331#endif 332 } 333}; 334} 335 336#endif //__ARCH_ARM_INSTS_STATICINST_HH__ | 292 } 293 294 inline Fault 295 disabledFault() const 296 { 297#if FULL_SYSTEM 298 return new UndefinedInstruction(); 299#else 300 return new UndefinedInstruction(machInst, false, mnemonic, true); 301#endif 302 } 303}; 304} 305 306#endif //__ARCH_ARM_INSTS_STATICINST_HH__ |