static_inst.hh (7400:f6c9b27c4dbe) static_inst.hh (7424:f5d721ddb509)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 33 unchanged lines hidden (view full) ---

42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "base/trace.hh"
46#include "cpu/static_inst.hh"
47
48namespace ArmISA
49{
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 33 unchanged lines hidden (view full) ---

42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "base/trace.hh"
46#include "cpu/static_inst.hh"
47
48namespace ArmISA
49{
50
50class ArmStaticInst : public StaticInst
51{
52 protected:
53 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
54 uint32_t type, uint32_t cfval) const;
55 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
56 uint32_t type, uint32_t cfval) const;
57
58 bool shift_carry_imm(uint32_t base, uint32_t shamt,
59 uint32_t type, uint32_t cfval) const;
60 bool shift_carry_rs(uint32_t base, uint32_t shamt,
61 uint32_t type, uint32_t cfval) const;
62
63 template<int width>
51class ArmStaticInst : public StaticInst
52{
53 protected:
54 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
55 uint32_t type, uint32_t cfval) const;
56 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
57 uint32_t type, uint32_t cfval) const;
58
59 bool shift_carry_imm(uint32_t base, uint32_t shamt,
60 uint32_t type, uint32_t cfval) const;
61 bool shift_carry_rs(uint32_t base, uint32_t shamt,
62 uint32_t type, uint32_t cfval) const;
63
64 template<int width>
64 static bool
65 static inline bool
65 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
66 {
67 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
68 if (bits(midRes, width) != bits(midRes, width - 1)) {
69 if (midRes > 0)
70 res = (LL(1) << (width - 1)) - 1;
71 else
72 res = -(LL(1) << (width - 1));
73 return true;
74 } else {
75 res = midRes;
76 return false;
77 }
78 }
79
66 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
67 {
68 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
69 if (bits(midRes, width) != bits(midRes, width - 1)) {
70 if (midRes > 0)
71 res = (LL(1) << (width - 1)) - 1;
72 else
73 res = -(LL(1) << (width - 1));
74 return true;
75 } else {
76 res = midRes;
77 return false;
78 }
79 }
80
80 static bool
81 static inline bool
81 satInt(int32_t &res, int64_t op, int width)
82 {
83 width--;
84 if (op >= (LL(1) << width)) {
85 res = (LL(1) << width) - 1;
86 return true;
87 } else if (op < -(LL(1) << width)) {
88 res = -(LL(1) << width);
89 return true;
90 } else {
91 res = op;
92 return false;
93 }
94 }
95
96 template<int width>
82 satInt(int32_t &res, int64_t op, int width)
83 {
84 width--;
85 if (op >= (LL(1) << width)) {
86 res = (LL(1) << width) - 1;
87 return true;
88 } else if (op < -(LL(1) << width)) {
89 res = -(LL(1) << width);
90 return true;
91 } else {
92 res = op;
93 return false;
94 }
95 }
96
97 template<int width>
97 static bool
98 static inline bool
98 uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
99 {
100 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
101 if (midRes >= (LL(1) << width)) {
102 res = (LL(1) << width) - 1;
103 return true;
104 } else if (midRes < 0) {
105 res = 0;
106 return true;
107 } else {
108 res = midRes;
109 return false;
110 }
111 }
112
99 uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
100 {
101 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
102 if (midRes >= (LL(1) << width)) {
103 res = (LL(1) << width) - 1;
104 return true;
105 } else if (midRes < 0) {
106 res = 0;
107 return true;
108 } else {
109 res = midRes;
110 return false;
111 }
112 }
113
113 static bool
114 static inline bool
114 uSatInt(int32_t &res, int64_t op, int width)
115 {
116 if (op >= (LL(1) << width)) {
117 res = (LL(1) << width) - 1;
118 return true;
119 } else if (op < 0) {
120 res = 0;
121 return true;

--- 27 unchanged lines hidden (view full) ---

149 void printDataInst(std::ostream &os, bool withImm) const;
150 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
151 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
152 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
153 uint32_t imm) const;
154
155 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
156
115 uSatInt(int32_t &res, int64_t op, int width)
116 {
117 if (op >= (LL(1) << width)) {
118 res = (LL(1) << width) - 1;
119 return true;
120 } else if (op < 0) {
121 res = 0;
122 return true;

--- 27 unchanged lines hidden (view full) ---

150 void printDataInst(std::ostream &os, bool withImm) const;
151 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
152 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
153 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
154 uint32_t imm) const;
155
156 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
157
157 static uint32_t
158 static inline uint32_t
158 cpsrWriteByInstr(CPSR cpsr, uint32_t val,
159 uint8_t byteMask, bool affectState, bool nmfi)
160 {
161 bool privileged = (cpsr.mode != MODE_USER);
162
163 uint32_t bitMask = 0;
164
165 if (bits(byteMask, 3)) {

--- 23 unchanged lines hidden (view full) ---

189
190 bool cpsr_f = cpsr.f;
191 uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
192 if (nmfi && !cpsr_f)
193 new_cpsr &= ~(1 << 6);
194 return new_cpsr;
195 }
196
159 cpsrWriteByInstr(CPSR cpsr, uint32_t val,
160 uint8_t byteMask, bool affectState, bool nmfi)
161 {
162 bool privileged = (cpsr.mode != MODE_USER);
163
164 uint32_t bitMask = 0;
165
166 if (bits(byteMask, 3)) {

--- 23 unchanged lines hidden (view full) ---

190
191 bool cpsr_f = cpsr.f;
192 uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
193 if (nmfi && !cpsr_f)
194 new_cpsr &= ~(1 << 6);
195 return new_cpsr;
196 }
197
197 static uint32_t
198 static inline uint32_t
198 spsrWriteByInstr(uint32_t spsr, uint32_t val,
199 uint8_t byteMask, bool affectState)
200 {
201 uint32_t bitMask = 0;
202
203 if (bits(byteMask, 3))
204 bitMask = bitMask | mask(31, 24);
205 if (bits(byteMask, 2))
206 bitMask = bitMask | mask(19, 16);
207 if (bits(byteMask, 1))
208 bitMask = bitMask | mask(15, 8);
209 if (bits(byteMask, 0))
210 bitMask = bitMask | mask(7, 0);
211
212 return ((spsr & ~bitMask) | (val & bitMask));
213 }
214
215 template<class XC>
199 spsrWriteByInstr(uint32_t spsr, uint32_t val,
200 uint8_t byteMask, bool affectState)
201 {
202 uint32_t bitMask = 0;
203
204 if (bits(byteMask, 3))
205 bitMask = bitMask | mask(31, 24);
206 if (bits(byteMask, 2))
207 bitMask = bitMask | mask(19, 16);
208 if (bits(byteMask, 1))
209 bitMask = bitMask | mask(15, 8);
210 if (bits(byteMask, 0))
211 bitMask = bitMask | mask(7, 0);
212
213 return ((spsr & ~bitMask) | (val & bitMask));
214 }
215
216 template<class XC>
216 static Addr
217 static inline Addr
217 readPC(XC *xc)
218 {
219 Addr pc = xc->readPC();
220 Addr tBit = pc & (ULL(1) << PcTBitShift);
221 if (tBit)
222 return pc + 4;
223 else
224 return pc + 8;
225 }
226
227 // Perform an regular branch.
228 template<class XC>
218 readPC(XC *xc)
219 {
220 Addr pc = xc->readPC();
221 Addr tBit = pc & (ULL(1) << PcTBitShift);
222 if (tBit)
223 return pc + 4;
224 else
225 return pc + 8;
226 }
227
228 // Perform an regular branch.
229 template<class XC>
229 static void
230 static inline void
230 setNextPC(XC *xc, Addr val)
231 {
232 Addr npc = xc->readNextPC();
233 if (npc & (ULL(1) << PcTBitShift)) {
234 val &= ~mask(1);
235 } else {
236 val &= ~mask(2);
237 }
238 xc->setNextPC((npc & PcModeMask) |
239 (val & ~PcModeMask));
240 }
241
242 template<class T>
231 setNextPC(XC *xc, Addr val)
232 {
233 Addr npc = xc->readNextPC();
234 if (npc & (ULL(1) << PcTBitShift)) {
235 val &= ~mask(1);
236 } else {
237 val &= ~mask(2);
238 }
239 xc->setNextPC((npc & PcModeMask) |
240 (val & ~PcModeMask));
241 }
242
243 template<class T>
243 static T
244 static inline T
244 cSwap(T val, bool big)
245 {
246 if (big) {
247 return gtobe(val);
248 } else {
249 return gtole(val);
250 }
251 }
252
253 // Perform an interworking branch.
254 template<class XC>
245 cSwap(T val, bool big)
246 {
247 if (big) {
248 return gtobe(val);
249 } else {
250 return gtole(val);
251 }
252 }
253
254 // Perform an interworking branch.
255 template<class XC>
255 static void
256 static inline void
256 setIWNextPC(XC *xc, Addr val)
257 {
258 Addr stateBits = xc->readPC() & PcModeMask;
259 Addr jBit = (ULL(1) << PcJBitShift);
260 Addr tBit = (ULL(1) << PcTBitShift);
261 bool thumbEE = (stateBits == (tBit | jBit));
262
263 Addr newPc = (val & ~PcModeMask);

--- 15 unchanged lines hidden (view full) ---

279 }
280 newPc = newPc | stateBits;
281 xc->setNextPC(newPc);
282 }
283
284 // Perform an interworking branch in ARM mode, a regular branch
285 // otherwise.
286 template<class XC>
257 setIWNextPC(XC *xc, Addr val)
258 {
259 Addr stateBits = xc->readPC() & PcModeMask;
260 Addr jBit = (ULL(1) << PcJBitShift);
261 Addr tBit = (ULL(1) << PcTBitShift);
262 bool thumbEE = (stateBits == (tBit | jBit));
263
264 Addr newPc = (val & ~PcModeMask);

--- 15 unchanged lines hidden (view full) ---

280 }
281 newPc = newPc | stateBits;
282 xc->setNextPC(newPc);
283 }
284
285 // Perform an interworking branch in ARM mode, a regular branch
286 // otherwise.
287 template<class XC>
287 static void
288 static inline void
288 setAIWNextPC(XC *xc, Addr val)
289 {
290 Addr stateBits = xc->readPC() & PcModeMask;
291 Addr jBit = (ULL(1) << PcJBitShift);
292 Addr tBit = (ULL(1) << PcTBitShift);
293 if (!jBit && !tBit) {
294 setIWNextPC(xc, val);
295 } else {
296 setNextPC(xc, val);
297 }
298 }
299};
300}
301
302#endif //__ARCH_ARM_INSTS_STATICINST_HH__
289 setAIWNextPC(XC *xc, Addr val)
290 {
291 Addr stateBits = xc->readPC() & PcModeMask;
292 Addr jBit = (ULL(1) << PcJBitShift);
293 Addr tBit = (ULL(1) << PcTBitShift);
294 if (!jBit && !tBit) {
295 setIWNextPC(xc, val);
296 } else {
297 setNextPC(xc, val);
298 }
299 }
300};
301}
302
303#endif //__ARCH_ARM_INSTS_STATICINST_HH__