static_inst.hh (7093:9832d4b070fc) static_inst.hh (7094:4d878c4a0c2b)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "base/trace.hh"
46#include "cpu/static_inst.hh"
47
48namespace ArmISA
49{
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "base/trace.hh"
46#include "cpu/static_inst.hh"
47
48namespace ArmISA
49{
50class ArmStaticInst : public StaticInst
50class ArmStaticInstBase : public StaticInst
51{
52 protected:
53 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
54 uint32_t type, uint32_t cfval) const;
55 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
56 uint32_t type, uint32_t cfval) const;
57
58 bool shift_carry_imm(uint32_t base, uint32_t shamt,
59 uint32_t type, uint32_t cfval) const;
60 bool shift_carry_rs(uint32_t base, uint32_t shamt,
61 uint32_t type, uint32_t cfval) const;
62
63 bool arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const;
64 bool arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const;
65
66 bool arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
67 bool arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
68
69 // Constructor
51{
52 protected:
53 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
54 uint32_t type, uint32_t cfval) const;
55 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
56 uint32_t type, uint32_t cfval) const;
57
58 bool shift_carry_imm(uint32_t base, uint32_t shamt,
59 uint32_t type, uint32_t cfval) const;
60 bool shift_carry_rs(uint32_t base, uint32_t shamt,
61 uint32_t type, uint32_t cfval) const;
62
63 bool arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const;
64 bool arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const;
65
66 bool arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
67 bool arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
68
69 // Constructor
70 ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
70 ArmStaticInstBase(const char *mnem, MachInst _machInst, OpClass __opClass)
71 : StaticInst(mnem, _machInst, __opClass)
72 {
73 }
74
75 /// Print a register name for disassembly given the unique
76 /// dependence tag number (FP or int).
77 void printReg(std::ostream &os, int reg) const;
78 void printMnemonic(std::ostream &os,

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141 template<class XC>
142 static void
143 setNextPC(XC *xc, Addr val)
144 {
145 xc->setNextPC((xc->readNextPC() & PcModeMask) |
146 (val & ~PcModeMask));
147 }
148};
71 : StaticInst(mnem, _machInst, __opClass)
72 {
73 }
74
75 /// Print a register name for disassembly given the unique
76 /// dependence tag number (FP or int).
77 void printReg(std::ostream &os, int reg) const;
78 void printMnemonic(std::ostream &os,

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141 template<class XC>
142 static void
143 setNextPC(XC *xc, Addr val)
144 {
145 xc->setNextPC((xc->readNextPC() & PcModeMask) |
146 (val & ~PcModeMask));
147 }
148};
149
150class ArmStaticInst : public ArmStaticInstBase
151{
152 protected:
153 ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
154 : ArmStaticInstBase(mnem, _machInst, __opClass)
155 {
156 }
157
158 template<class XC>
159 static void
160 setNextPC(XC *xc, Addr val)
161 {
162 xc->setNextPC((xc->readNextPC() & PcModeMask) |
163 (val & ~PcModeMask));
164 }
165};
166
167class ArmInterWorking : public ArmStaticInstBase
168{
169 protected:
170 ArmInterWorking(const char *mnem, MachInst _machInst, OpClass __opClass)
171 : ArmStaticInstBase(mnem, _machInst, __opClass)
172 {
173 }
174
175 template<class XC>
176 static void
177 setNextPC(XC *xc, Addr val)
178 {
179 Addr stateBits = xc->readPC() & PcModeMask;
180 Addr jBit = (ULL(1) << PcJBitShift);
181 Addr tBit = (ULL(1) << PcTBitShift);
182 bool thumbEE = (stateBits == (tBit | jBit));
183
184 Addr newPc = (val & ~PcModeMask);
185 if (thumbEE) {
186 if (bits(newPc, 0)) {
187 warn("Bad thumbEE interworking branch address %#x.\n", newPc);
188 } else {
189 newPc = newPc & ~mask(1);
190 }
191 } else {
192 if (bits(newPc, 0)) {
193 stateBits = tBit;
194 newPc = newPc & ~mask(1);
195 } else if (!bits(newPc, 1)) {
196 stateBits = 0;
197 } else {
198 warn("Bad interworking branch address %#x.\n", newPc);
199 }
200 }
201 newPc = newPc | stateBits;
202 xc->setNextPC(newPc);
203 }
204};
149}
150
151#endif //__ARCH_ARM_INSTS_STATICINST_HH__
205}
206
207#endif //__ARCH_ARM_INSTS_STATICINST_HH__