1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__ 43#define __ARCH_ARM_INSTS_STATICINST_HH__ 44 45#include "base/trace.hh" 46#include "cpu/static_inst.hh" 47 48namespace ArmISA 49{ 50class ArmStaticInst : public StaticInst 51{ 52 protected:
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58 int32_t shift_rm_imm(uint32_t base, uint32_t shamt, 59 uint32_t type, uint32_t cfval) const; 60 int32_t shift_rm_rs(uint32_t base, uint32_t shamt, 61 uint32_t type, uint32_t cfval) const; 62 63 bool shift_carry_imm(uint32_t base, uint32_t shamt, 64 uint32_t type, uint32_t cfval) const; 65 bool shift_carry_rs(uint32_t base, uint32_t shamt, 66 uint32_t type, uint32_t cfval) const; 67 68 template<int width> 69 static bool 70 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) 71 { 72 int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 73 if (bits(midRes, width) != bits(midRes, width - 1)) { 74 if (midRes > 0) 75 res = (LL(1) << (width - 1)) - 1; 76 else 77 res = -(LL(1) << (width - 1)); 78 return true; 79 } else { 80 res = midRes; 81 return false; 82 } 83 } 84 85 static bool 86 satInt(int32_t &res, int64_t op, int width) 87 { 88 width--; 89 if (op >= (LL(1) << width)) { 90 res = (LL(1) << width) - 1; 91 return true; 92 } else if (op < -(LL(1) << width)) { 93 res = -(LL(1) << width); 94 return true; 95 } else { 96 res = op; 97 return false; 98 } 99 } 100 101 template<int width> 102 static bool 103 uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) 104 { 105 int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 106 if (midRes >= (LL(1) << width)) { 107 res = (LL(1) << width) - 1; 108 return true; 109 } else if (midRes < 0) { 110 res = 0; 111 return true; 112 } else { 113 res = midRes; 114 return false; 115 } 116 } 117 118 static bool 119 uSatInt(int32_t &res, int64_t op, int width) 120 { 121 if (op >= (LL(1) << width)) { 122 res = (LL(1) << width) - 1; 123 return true; 124 } else if (op < 0) { 125 res = 0; 126 return true; 127 } else { 128 res = op; 129 return false; 130 } 131 } 132 133 // Constructor 134 ArmStaticInst(const char *mnem, ExtMachInst _machInst, 135 OpClass __opClass) 136 : StaticInst(mnem, _machInst, __opClass) 137 { 138 } 139 140 /// Print a register name for disassembly given the unique 141 /// dependence tag number (FP or int). 142 void printReg(std::ostream &os, int reg) const; 143 void printMnemonic(std::ostream &os, 144 const std::string &suffix = "", 145 bool withPred = true) const; 146 void printMemSymbol(std::ostream &os, const SymbolTable *symtab, 147 const std::string &prefix, const Addr addr, 148 const std::string &suffix) const; 149 void printShiftOperand(std::ostream &os, IntRegIndex rm, 150 bool immShift, uint32_t shiftAmt, 151 IntRegIndex rs, ArmShiftType type) const; 152 153 154 void printDataInst(std::ostream &os, bool withImm) const; 155 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 156 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 157 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 158 uint32_t imm) const; 159 160 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 161 162 static uint32_t 163 cpsrWriteByInstr(CPSR cpsr, uint32_t val, 164 uint8_t byteMask, bool affectState) 165 { 166 bool privileged = (cpsr.mode != MODE_USER); 167 168 uint32_t bitMask = 0; 169 170 if (bits(byteMask, 3)) { 171 unsigned lowIdx = affectState ? 24 : 27; 172 bitMask = bitMask | mask(31, lowIdx); 173 } 174 if (bits(byteMask, 2)) { 175 bitMask = bitMask | mask(19, 16); 176 } 177 if (bits(byteMask, 1)) { 178 unsigned highIdx = affectState ? 15 : 9; 179 unsigned lowIdx = privileged ? 8 : 9; 180 bitMask = bitMask | mask(highIdx, lowIdx); 181 } 182 if (bits(byteMask, 0)) { 183 if (privileged) { 184 bitMask = bitMask | mask(7, 6); 185 if (!badMode((OperatingMode)(val & mask(5)))) { 186 bitMask = bitMask | mask(5); 187 } else { 188 warn_once("Ignoring write of bad mode to CPSR.\n"); 189 } 190 } 191 if (affectState) 192 bitMask = bitMask | (1 << 5); 193 } 194 195 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask); 196 } 197 198 static uint32_t 199 spsrWriteByInstr(uint32_t spsr, uint32_t val, 200 uint8_t byteMask, bool affectState) 201 { 202 uint32_t bitMask = 0; 203 204 if (bits(byteMask, 3)) 205 bitMask = bitMask | mask(31, 24); 206 if (bits(byteMask, 2)) 207 bitMask = bitMask | mask(19, 16); 208 if (bits(byteMask, 1)) 209 bitMask = bitMask | mask(15, 8); 210 if (bits(byteMask, 0)) 211 bitMask = bitMask | mask(7, 0); 212 213 return ((spsr & ~bitMask) | (val & bitMask)); 214 } 215 216 template<class XC> 217 static Addr 218 readPC(XC *xc) 219 { 220 Addr pc = xc->readPC(); 221 Addr tBit = pc & (ULL(1) << PcTBitShift); 222 if (tBit) 223 return pc + 4; 224 else 225 return pc + 8; 226 } 227 228 // Perform an regular branch. 229 template<class XC> 230 static void 231 setNextPC(XC *xc, Addr val) 232 { 233 Addr npc = xc->readNextPC(); 234 if (npc & (ULL(1) << PcTBitShift)) { 235 val &= ~mask(1); 236 } else { 237 val &= ~mask(2); 238 } 239 xc->setNextPC((npc & PcModeMask) | 240 (val & ~PcModeMask)); 241 } 242 243 template<class T> 244 static T 245 cSwap(T val, bool big) 246 { 247 if (big) { 248 return gtobe(val); 249 } else { 250 return gtole(val); 251 } 252 } 253 254 // Perform an interworking branch. 255 template<class XC> 256 static void 257 setIWNextPC(XC *xc, Addr val) 258 { 259 Addr stateBits = xc->readPC() & PcModeMask; 260 Addr jBit = (ULL(1) << PcJBitShift); 261 Addr tBit = (ULL(1) << PcTBitShift); 262 bool thumbEE = (stateBits == (tBit | jBit)); 263 264 Addr newPc = (val & ~PcModeMask); 265 if (thumbEE) { 266 if (bits(newPc, 0)) { 267 newPc = newPc & ~mask(1); 268 } else { 269 panic("Bad thumbEE interworking branch address %#x.\n", newPc); 270 } 271 } else { 272 if (bits(newPc, 0)) { 273 stateBits = tBit; 274 newPc = newPc & ~mask(1); 275 } else if (!bits(newPc, 1)) { 276 stateBits = 0; 277 } else { 278 warn("Bad interworking branch address %#x.\n", newPc); 279 } 280 } 281 newPc = newPc | stateBits; 282 xc->setNextPC(newPc); 283 } 284 285 // Perform an interworking branch in ARM mode, a regular branch 286 // otherwise. 287 template<class XC> 288 static void 289 setAIWNextPC(XC *xc, Addr val) 290 { 291 Addr stateBits = xc->readPC() & PcModeMask; 292 Addr jBit = (ULL(1) << PcJBitShift); 293 Addr tBit = (ULL(1) << PcTBitShift); 294 if (!jBit && !tBit) { 295 setIWNextPC(xc, val); 296 } else { 297 setNextPC(xc, val); 298 } 299 } 300}; 301} 302 303#endif //__ARCH_ARM_INSTS_STATICINST_HH__
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