1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "base/trace.hh"
46#include "cpu/static_inst.hh"
47
48namespace ArmISA
49{
50class ArmStaticInstBase : public StaticInst
51{
52 protected:
53 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
54 uint32_t type, uint32_t cfval) const;
55 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
56 uint32_t type, uint32_t cfval) const;
57
58 bool shift_carry_imm(uint32_t base, uint32_t shamt,
59 uint32_t type, uint32_t cfval) const;
60 bool shift_carry_rs(uint32_t base, uint32_t shamt,
61 uint32_t type, uint32_t cfval) const;
62
63 bool arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const;
64 bool arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const;
65
66 bool arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
67 bool arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
68
69 // Constructor
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "base/trace.hh"
46#include "cpu/static_inst.hh"
47
48namespace ArmISA
49{
50class ArmStaticInstBase : public StaticInst
51{
52 protected:
53 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
54 uint32_t type, uint32_t cfval) const;
55 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
56 uint32_t type, uint32_t cfval) const;
57
58 bool shift_carry_imm(uint32_t base, uint32_t shamt,
59 uint32_t type, uint32_t cfval) const;
60 bool shift_carry_rs(uint32_t base, uint32_t shamt,
61 uint32_t type, uint32_t cfval) const;
62
63 bool arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const;
64 bool arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const;
65
66 bool arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
67 bool arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
68
69 // Constructor
|
70 ArmStaticInstBase(const char *mnem, MachInst _machInst, OpClass __opClass)
| 70 ArmStaticInstBase(const char *mnem, ExtMachInst _machInst,
71 OpClass __opClass)
|
71 : StaticInst(mnem, _machInst, __opClass)
72 {
73 }
74
75 /// Print a register name for disassembly given the unique
76 /// dependence tag number (FP or int).
77 void printReg(std::ostream &os, int reg) const;
78 void printMnemonic(std::ostream &os,
79 const std::string &suffix = "",
80 bool withPred = true) const;
81 void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
82 const std::string &prefix, const Addr addr,
83 const std::string &suffix) const;
84 void printShiftOperand(std::ostream &os) const;
85
86
87 void printDataInst(std::ostream &os, bool withImm) const;
88
89 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
90
91 static uint32_t
92 cpsrWriteByInstr(CPSR cpsr, uint32_t val,
93 uint8_t byteMask, bool affectState)
94 {
95 bool privileged = (cpsr.mode != MODE_USER);
96
97 uint32_t bitMask = 0;
98
99 if (bits(byteMask, 3)) {
100 unsigned lowIdx = affectState ? 24 : 27;
101 bitMask = bitMask | mask(31, lowIdx);
102 }
103 if (bits(byteMask, 2)) {
104 bitMask = bitMask | mask(19, 16);
105 }
106 if (bits(byteMask, 1)) {
107 unsigned highIdx = affectState ? 15 : 9;
108 unsigned lowIdx = privileged ? 8 : 9;
109 bitMask = bitMask | mask(highIdx, lowIdx);
110 }
111 if (bits(byteMask, 0)) {
112 if (privileged) {
113 bitMask = bitMask | mask(7, 6);
114 bitMask = bitMask | mask(5);
115 }
116 if (affectState)
117 bitMask = bitMask | (1 << 5);
118 }
119
120 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
121 }
122
123 static uint32_t
124 spsrWriteByInstr(uint32_t spsr, uint32_t val,
125 uint8_t byteMask, bool affectState)
126 {
127 uint32_t bitMask = 0;
128
129 if (bits(byteMask, 3))
130 bitMask = bitMask | mask(31, 24);
131 if (bits(byteMask, 2))
132 bitMask = bitMask | mask(19, 16);
133 if (bits(byteMask, 1))
134 bitMask = bitMask | mask(15, 8);
135 if (bits(byteMask, 0))
136 bitMask = bitMask | mask(7, 0);
137
138 return ((spsr & ~bitMask) | (val & bitMask));
139 }
140
141 template<class XC>
142 static void
143 setNextPC(XC *xc, Addr val)
144 {
145 xc->setNextPC((xc->readNextPC() & PcModeMask) |
146 (val & ~PcModeMask));
147 }
148};
149
150class ArmStaticInst : public ArmStaticInstBase
151{
152 protected:
| 72 : StaticInst(mnem, _machInst, __opClass)
73 {
74 }
75
76 /// Print a register name for disassembly given the unique
77 /// dependence tag number (FP or int).
78 void printReg(std::ostream &os, int reg) const;
79 void printMnemonic(std::ostream &os,
80 const std::string &suffix = "",
81 bool withPred = true) const;
82 void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
83 const std::string &prefix, const Addr addr,
84 const std::string &suffix) const;
85 void printShiftOperand(std::ostream &os) const;
86
87
88 void printDataInst(std::ostream &os, bool withImm) const;
89
90 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
91
92 static uint32_t
93 cpsrWriteByInstr(CPSR cpsr, uint32_t val,
94 uint8_t byteMask, bool affectState)
95 {
96 bool privileged = (cpsr.mode != MODE_USER);
97
98 uint32_t bitMask = 0;
99
100 if (bits(byteMask, 3)) {
101 unsigned lowIdx = affectState ? 24 : 27;
102 bitMask = bitMask | mask(31, lowIdx);
103 }
104 if (bits(byteMask, 2)) {
105 bitMask = bitMask | mask(19, 16);
106 }
107 if (bits(byteMask, 1)) {
108 unsigned highIdx = affectState ? 15 : 9;
109 unsigned lowIdx = privileged ? 8 : 9;
110 bitMask = bitMask | mask(highIdx, lowIdx);
111 }
112 if (bits(byteMask, 0)) {
113 if (privileged) {
114 bitMask = bitMask | mask(7, 6);
115 bitMask = bitMask | mask(5);
116 }
117 if (affectState)
118 bitMask = bitMask | (1 << 5);
119 }
120
121 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
122 }
123
124 static uint32_t
125 spsrWriteByInstr(uint32_t spsr, uint32_t val,
126 uint8_t byteMask, bool affectState)
127 {
128 uint32_t bitMask = 0;
129
130 if (bits(byteMask, 3))
131 bitMask = bitMask | mask(31, 24);
132 if (bits(byteMask, 2))
133 bitMask = bitMask | mask(19, 16);
134 if (bits(byteMask, 1))
135 bitMask = bitMask | mask(15, 8);
136 if (bits(byteMask, 0))
137 bitMask = bitMask | mask(7, 0);
138
139 return ((spsr & ~bitMask) | (val & bitMask));
140 }
141
142 template<class XC>
143 static void
144 setNextPC(XC *xc, Addr val)
145 {
146 xc->setNextPC((xc->readNextPC() & PcModeMask) |
147 (val & ~PcModeMask));
148 }
149};
150
151class ArmStaticInst : public ArmStaticInstBase
152{
153 protected:
|
153 ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
| 154 ArmStaticInst(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
|
154 : ArmStaticInstBase(mnem, _machInst, __opClass)
155 {
156 }
157
158 template<class XC>
159 static void
160 setNextPC(XC *xc, Addr val)
161 {
162 xc->setNextPC((xc->readNextPC() & PcModeMask) |
163 (val & ~PcModeMask));
164 }
165};
166
167class ArmInterWorking : public ArmStaticInstBase
168{
169 protected:
| 155 : ArmStaticInstBase(mnem, _machInst, __opClass)
156 {
157 }
158
159 template<class XC>
160 static void
161 setNextPC(XC *xc, Addr val)
162 {
163 xc->setNextPC((xc->readNextPC() & PcModeMask) |
164 (val & ~PcModeMask));
165 }
166};
167
168class ArmInterWorking : public ArmStaticInstBase
169{
170 protected:
|
170 ArmInterWorking(const char *mnem, MachInst _machInst, OpClass __opClass)
| 171 ArmInterWorking(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
|
171 : ArmStaticInstBase(mnem, _machInst, __opClass)
172 {
173 }
174
175 template<class XC>
176 static void
177 setNextPC(XC *xc, Addr val)
178 {
179 Addr stateBits = xc->readPC() & PcModeMask;
180 Addr jBit = (ULL(1) << PcJBitShift);
181 Addr tBit = (ULL(1) << PcTBitShift);
182 bool thumbEE = (stateBits == (tBit | jBit));
183
184 Addr newPc = (val & ~PcModeMask);
185 if (thumbEE) {
186 if (bits(newPc, 0)) {
187 warn("Bad thumbEE interworking branch address %#x.\n", newPc);
188 } else {
189 newPc = newPc & ~mask(1);
190 }
191 } else {
192 if (bits(newPc, 0)) {
193 stateBits = tBit;
194 newPc = newPc & ~mask(1);
195 } else if (!bits(newPc, 1)) {
196 stateBits = 0;
197 } else {
198 warn("Bad interworking branch address %#x.\n", newPc);
199 }
200 }
201 newPc = newPc | stateBits;
202 xc->setNextPC(newPc);
203 }
204};
205}
206
207#endif //__ARCH_ARM_INSTS_STATICINST_HH__
| 172 : ArmStaticInstBase(mnem, _machInst, __opClass)
173 {
174 }
175
176 template<class XC>
177 static void
178 setNextPC(XC *xc, Addr val)
179 {
180 Addr stateBits = xc->readPC() & PcModeMask;
181 Addr jBit = (ULL(1) << PcJBitShift);
182 Addr tBit = (ULL(1) << PcTBitShift);
183 bool thumbEE = (stateBits == (tBit | jBit));
184
185 Addr newPc = (val & ~PcModeMask);
186 if (thumbEE) {
187 if (bits(newPc, 0)) {
188 warn("Bad thumbEE interworking branch address %#x.\n", newPc);
189 } else {
190 newPc = newPc & ~mask(1);
191 }
192 } else {
193 if (bits(newPc, 0)) {
194 stateBits = tBit;
195 newPc = newPc & ~mask(1);
196 } else if (!bits(newPc, 1)) {
197 stateBits = 0;
198 } else {
199 warn("Bad interworking branch address %#x.\n", newPc);
200 }
201 }
202 newPc = newPc | stateBits;
203 xc->setNextPC(newPc);
204 }
205};
206}
207
208#endif //__ARCH_ARM_INSTS_STATICINST_HH__
|