2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Stephen Hines
28 */
29#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
30#define __ARCH_ARM_INSTS_STATICINST_HH__
31
32#include "base/trace.hh"
33#include "cpu/static_inst.hh"
34
35namespace ArmISA
36{
37class ArmStaticInst : public StaticInst
38{
39 protected:
40 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
41 uint32_t type, uint32_t cfval) const;
42 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
43 uint32_t type, uint32_t cfval) const;
44
45 bool shift_carry_imm(uint32_t base, uint32_t shamt,
46 uint32_t type, uint32_t cfval) const;
47 bool shift_carry_rs(uint32_t base, uint32_t shamt,
48 uint32_t type, uint32_t cfval) const;
49
50 bool arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const;
51 bool arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const;
52
53 bool arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
54 bool arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
55
56 // Constructor
57 ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
58 : StaticInst(mnem, _machInst, __opClass)
59 {
60 }
61
62 /// Print a register name for disassembly given the unique
63 /// dependence tag number (FP or int).
64 void printReg(std::ostream &os, int reg) const;
65 void printMnemonic(std::ostream &os,
66 const std::string &suffix = "",
67 bool withPred = true) const;
68 void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
69 const std::string &prefix, const Addr addr,
70 const std::string &suffix) const;
71 void printShiftOperand(std::ostream &os) const;
72
73
74 void printDataInst(std::ostream &os, bool withImm) const;
75
76 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
77
78 static uint32_t
79 cpsrWriteByInstr(CPSR cpsr, uint32_t val,
80 uint8_t byteMask, bool affectState)
81 {
82 bool privileged = (cpsr.mode != MODE_USER);
83
84 uint32_t bitMask = 0;
85
86 if (bits(byteMask, 3)) {
87 unsigned lowIdx = affectState ? 24 : 27;
88 bitMask = bitMask | mask(31, lowIdx);
89 }
90 if (bits(byteMask, 2)) {
91 bitMask = bitMask | mask(19, 16);
92 }
93 if (bits(byteMask, 1)) {
94 unsigned highIdx = affectState ? 15 : 9;
95 unsigned lowIdx = privileged ? 8 : 9;
96 bitMask = bitMask | mask(highIdx, lowIdx);
97 }
98 if (bits(byteMask, 0)) {
99 if (privileged) {
100 bitMask = bitMask | mask(7, 6);
101 bitMask = bitMask | mask(5);
102 }
103 if (affectState)
104 bitMask = bitMask | (1 << 5);
105 }
106
107 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
108 }
109
110 static uint32_t
111 spsrWriteByInstr(uint32_t spsr, uint32_t val,
112 uint8_t byteMask, bool affectState)
113 {
114 uint32_t bitMask = 0;
115
116 if (bits(byteMask, 3))
117 bitMask = bitMask | mask(31, 24);
118 if (bits(byteMask, 2))
119 bitMask = bitMask | mask(19, 16);
120 if (bits(byteMask, 1))
121 bitMask = bitMask | mask(15, 8);
122 if (bits(byteMask, 0))
123 bitMask = bitMask | mask(7, 0);
124
125 return ((spsr & ~bitMask) | (val & bitMask));
126 }
| 15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "base/trace.hh"
46#include "cpu/static_inst.hh"
47
48namespace ArmISA
49{
50class ArmStaticInst : public StaticInst
51{
52 protected:
53 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
54 uint32_t type, uint32_t cfval) const;
55 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
56 uint32_t type, uint32_t cfval) const;
57
58 bool shift_carry_imm(uint32_t base, uint32_t shamt,
59 uint32_t type, uint32_t cfval) const;
60 bool shift_carry_rs(uint32_t base, uint32_t shamt,
61 uint32_t type, uint32_t cfval) const;
62
63 bool arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const;
64 bool arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const;
65
66 bool arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
67 bool arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const;
68
69 // Constructor
70 ArmStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
71 : StaticInst(mnem, _machInst, __opClass)
72 {
73 }
74
75 /// Print a register name for disassembly given the unique
76 /// dependence tag number (FP or int).
77 void printReg(std::ostream &os, int reg) const;
78 void printMnemonic(std::ostream &os,
79 const std::string &suffix = "",
80 bool withPred = true) const;
81 void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
82 const std::string &prefix, const Addr addr,
83 const std::string &suffix) const;
84 void printShiftOperand(std::ostream &os) const;
85
86
87 void printDataInst(std::ostream &os, bool withImm) const;
88
89 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
90
91 static uint32_t
92 cpsrWriteByInstr(CPSR cpsr, uint32_t val,
93 uint8_t byteMask, bool affectState)
94 {
95 bool privileged = (cpsr.mode != MODE_USER);
96
97 uint32_t bitMask = 0;
98
99 if (bits(byteMask, 3)) {
100 unsigned lowIdx = affectState ? 24 : 27;
101 bitMask = bitMask | mask(31, lowIdx);
102 }
103 if (bits(byteMask, 2)) {
104 bitMask = bitMask | mask(19, 16);
105 }
106 if (bits(byteMask, 1)) {
107 unsigned highIdx = affectState ? 15 : 9;
108 unsigned lowIdx = privileged ? 8 : 9;
109 bitMask = bitMask | mask(highIdx, lowIdx);
110 }
111 if (bits(byteMask, 0)) {
112 if (privileged) {
113 bitMask = bitMask | mask(7, 6);
114 bitMask = bitMask | mask(5);
115 }
116 if (affectState)
117 bitMask = bitMask | (1 << 5);
118 }
119
120 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
121 }
122
123 static uint32_t
124 spsrWriteByInstr(uint32_t spsr, uint32_t val,
125 uint8_t byteMask, bool affectState)
126 {
127 uint32_t bitMask = 0;
128
129 if (bits(byteMask, 3))
130 bitMask = bitMask | mask(31, 24);
131 if (bits(byteMask, 2))
132 bitMask = bitMask | mask(19, 16);
133 if (bits(byteMask, 1))
134 bitMask = bitMask | mask(15, 8);
135 if (bits(byteMask, 0))
136 bitMask = bitMask | mask(7, 0);
137
138 return ((spsr & ~bitMask) | (val & bitMask));
139 }
|