1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include <memory>
46
47#include "arch/arm/faults.hh"
48#include "arch/arm/utility.hh"
49#include "arch/arm/system.hh"
50#include "base/trace.hh"
| 1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include <memory>
46
47#include "arch/arm/faults.hh"
48#include "arch/arm/utility.hh"
49#include "arch/arm/system.hh"
50#include "base/trace.hh"
|
51#include "cpu/static_inst.hh"
52#include "sim/byteswap.hh"
53#include "sim/full_system.hh"
54
55namespace ArmISA
56{
57
58class ArmStaticInst : public StaticInst
59{
60 protected:
61 bool aarch64;
62 uint8_t intWidth;
63
64 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
65 uint32_t type, uint32_t cfval) const;
66 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
67 uint32_t type, uint32_t cfval) const;
68
69 bool shift_carry_imm(uint32_t base, uint32_t shamt,
70 uint32_t type, uint32_t cfval) const;
71 bool shift_carry_rs(uint32_t base, uint32_t shamt,
72 uint32_t type, uint32_t cfval) const;
73
74 int64_t shiftReg64(uint64_t base, uint64_t shiftAmt,
75 ArmShiftType type, uint8_t width) const;
76 int64_t extendReg64(uint64_t base, ArmExtendType type,
77 uint64_t shiftAmt, uint8_t width) const;
78
79 template<int width>
80 static inline bool
81 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
82 {
83 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
84 if (bits(midRes, width) != bits(midRes, width - 1)) {
85 if (midRes > 0)
86 res = (LL(1) << (width - 1)) - 1;
87 else
88 res = -(LL(1) << (width - 1));
89 return true;
90 } else {
91 res = midRes;
92 return false;
93 }
94 }
95
96 static inline bool
97 satInt(int32_t &res, int64_t op, int width)
98 {
99 width--;
100 if (op >= (LL(1) << width)) {
101 res = (LL(1) << width) - 1;
102 return true;
103 } else if (op < -(LL(1) << width)) {
104 res = -(LL(1) << width);
105 return true;
106 } else {
107 res = op;
108 return false;
109 }
110 }
111
112 template<int width>
113 static inline bool
114 uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
115 {
116 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
117 if (midRes >= (LL(1) << width)) {
118 res = (LL(1) << width) - 1;
119 return true;
120 } else if (midRes < 0) {
121 res = 0;
122 return true;
123 } else {
124 res = midRes;
125 return false;
126 }
127 }
128
129 static inline bool
130 uSatInt(int32_t &res, int64_t op, int width)
131 {
132 if (op >= (LL(1) << width)) {
133 res = (LL(1) << width) - 1;
134 return true;
135 } else if (op < 0) {
136 res = 0;
137 return true;
138 } else {
139 res = op;
140 return false;
141 }
142 }
143
144 // Constructor
145 ArmStaticInst(const char *mnem, ExtMachInst _machInst,
146 OpClass __opClass)
147 : StaticInst(mnem, _machInst, __opClass)
148 {
149 aarch64 = machInst.aarch64;
150 if (bits(machInst, 28, 24) == 0x10)
151 intWidth = 64; // Force 64-bit width for ADR/ADRP
152 else
153 intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32;
154 }
155
156 /// Print a register name for disassembly given the unique
157 /// dependence tag number (FP or int).
158 void printIntReg(std::ostream &os, RegIndex reg_idx) const;
159 void printFloatReg(std::ostream &os, RegIndex reg_idx) const;
160 void printVecReg(std::ostream &os, RegIndex reg_idx) const;
161 void printCCReg(std::ostream &os, RegIndex reg_idx) const;
162 void printMiscReg(std::ostream &os, RegIndex reg_idx) const;
163 void printMnemonic(std::ostream &os,
164 const std::string &suffix = "",
165 bool withPred = true,
166 bool withCond64 = false,
167 ConditionCode cond64 = COND_UC) const;
168 void printTarget(std::ostream &os, Addr target,
169 const SymbolTable *symtab) const;
170 void printCondition(std::ostream &os, unsigned code,
171 bool noImplicit=false) const;
172 void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
173 const std::string &prefix, const Addr addr,
174 const std::string &suffix) const;
175 void printShiftOperand(std::ostream &os, IntRegIndex rm,
176 bool immShift, uint32_t shiftAmt,
177 IntRegIndex rs, ArmShiftType type) const;
178 void printExtendOperand(bool firstOperand, std::ostream &os,
179 IntRegIndex rm, ArmExtendType type,
180 int64_t shiftAmt) const;
181
182
183 void printDataInst(std::ostream &os, bool withImm) const;
184 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
185 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
186 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
187 uint64_t imm) const;
188
189 void
190 advancePC(PCState &pcState) const
191 {
192 pcState.advance();
193 }
194
195 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
196
197 static inline uint32_t
198 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,
199 uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
200 {
201 bool privileged = (cpsr.mode != MODE_USER);
202 bool haveVirt = ArmSystem::haveVirtualization(tc);
203 bool haveSecurity = ArmSystem::haveSecurity(tc);
204 bool isSecure = inSecureState(scr, cpsr) || !haveSecurity;
205
206 uint32_t bitMask = 0;
207
208 if (bits(byteMask, 3)) {
209 unsigned lowIdx = affectState ? 24 : 27;
210 bitMask = bitMask | mask(31, lowIdx);
211 }
212 if (bits(byteMask, 2)) {
213 bitMask = bitMask | mask(19, 16);
214 }
215 if (bits(byteMask, 1)) {
216 unsigned highIdx = affectState ? 15 : 9;
217 unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt))
218 ? 8 : 9;
219 bitMask = bitMask | mask(highIdx, lowIdx);
220 }
221 if (bits(byteMask, 0)) {
222 if (privileged) {
223 bitMask |= 1 << 7;
224 if ( (!nmfi || !((val >> 6) & 0x1)) &&
225 (isSecure || scr.fw || haveVirt) ) {
226 bitMask |= 1 << 6;
227 }
228 // Now check the new mode is allowed
229 OperatingMode newMode = (OperatingMode) (val & mask(5));
230 OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
231 if (!badMode(newMode)) {
232 bool validModeChange = true;
233 // Check for attempts to enter modes only permitted in
234 // Secure state from Non-secure state. These are Monitor
235 // mode ('10110'), and FIQ mode ('10001') if the Security
236 // Extensions have reserved it.
237 if (!isSecure && newMode == MODE_MON)
238 validModeChange = false;
239 if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1')
240 validModeChange = false;
241 // There is no Hyp mode ('11010') in Secure state, so that
242 // is UNPREDICTABLE
243 if (scr.ns == '0' && newMode == MODE_HYP)
244 validModeChange = false;
245 // Cannot move into Hyp mode directly from a Non-secure
246 // PL1 mode
247 if (!isSecure && oldMode != MODE_HYP && newMode == MODE_HYP)
248 validModeChange = false;
249 // Cannot move out of Hyp mode with this function except
250 // on an exception return
251 if (oldMode == MODE_HYP && newMode != MODE_HYP && !affectState)
252 validModeChange = false;
253 // Must not change to 64 bit when running in 32 bit mode
254 if (!opModeIs64(oldMode) && opModeIs64(newMode))
255 validModeChange = false;
256
257 // If we passed all of the above then set the bit mask to
258 // copy the mode accross
259 if (validModeChange) {
260 bitMask = bitMask | mask(5);
261 } else {
262 warn_once("Illegal change to CPSR mode attempted\n");
263 }
264 } else {
265 warn_once("Ignoring write of bad mode to CPSR.\n");
266 }
267 }
268 if (affectState)
269 bitMask = bitMask | (1 << 5);
270 }
271
272 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
273 }
274
275 static inline uint32_t
276 spsrWriteByInstr(uint32_t spsr, uint32_t val,
277 uint8_t byteMask, bool affectState)
278 {
279 uint32_t bitMask = 0;
280
281 if (bits(byteMask, 3))
282 bitMask = bitMask | mask(31, 24);
283 if (bits(byteMask, 2))
284 bitMask = bitMask | mask(19, 16);
285 if (bits(byteMask, 1))
286 bitMask = bitMask | mask(15, 8);
287 if (bits(byteMask, 0))
288 bitMask = bitMask | mask(7, 0);
289
290 return ((spsr & ~bitMask) | (val & bitMask));
291 }
292
| 52#include "cpu/static_inst.hh"
53#include "sim/byteswap.hh"
54#include "sim/full_system.hh"
55
56namespace ArmISA
57{
58
59class ArmStaticInst : public StaticInst
60{
61 protected:
62 bool aarch64;
63 uint8_t intWidth;
64
65 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
66 uint32_t type, uint32_t cfval) const;
67 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
68 uint32_t type, uint32_t cfval) const;
69
70 bool shift_carry_imm(uint32_t base, uint32_t shamt,
71 uint32_t type, uint32_t cfval) const;
72 bool shift_carry_rs(uint32_t base, uint32_t shamt,
73 uint32_t type, uint32_t cfval) const;
74
75 int64_t shiftReg64(uint64_t base, uint64_t shiftAmt,
76 ArmShiftType type, uint8_t width) const;
77 int64_t extendReg64(uint64_t base, ArmExtendType type,
78 uint64_t shiftAmt, uint8_t width) const;
79
80 template<int width>
81 static inline bool
82 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
83 {
84 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
85 if (bits(midRes, width) != bits(midRes, width - 1)) {
86 if (midRes > 0)
87 res = (LL(1) << (width - 1)) - 1;
88 else
89 res = -(LL(1) << (width - 1));
90 return true;
91 } else {
92 res = midRes;
93 return false;
94 }
95 }
96
97 static inline bool
98 satInt(int32_t &res, int64_t op, int width)
99 {
100 width--;
101 if (op >= (LL(1) << width)) {
102 res = (LL(1) << width) - 1;
103 return true;
104 } else if (op < -(LL(1) << width)) {
105 res = -(LL(1) << width);
106 return true;
107 } else {
108 res = op;
109 return false;
110 }
111 }
112
113 template<int width>
114 static inline bool
115 uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
116 {
117 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
118 if (midRes >= (LL(1) << width)) {
119 res = (LL(1) << width) - 1;
120 return true;
121 } else if (midRes < 0) {
122 res = 0;
123 return true;
124 } else {
125 res = midRes;
126 return false;
127 }
128 }
129
130 static inline bool
131 uSatInt(int32_t &res, int64_t op, int width)
132 {
133 if (op >= (LL(1) << width)) {
134 res = (LL(1) << width) - 1;
135 return true;
136 } else if (op < 0) {
137 res = 0;
138 return true;
139 } else {
140 res = op;
141 return false;
142 }
143 }
144
145 // Constructor
146 ArmStaticInst(const char *mnem, ExtMachInst _machInst,
147 OpClass __opClass)
148 : StaticInst(mnem, _machInst, __opClass)
149 {
150 aarch64 = machInst.aarch64;
151 if (bits(machInst, 28, 24) == 0x10)
152 intWidth = 64; // Force 64-bit width for ADR/ADRP
153 else
154 intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32;
155 }
156
157 /// Print a register name for disassembly given the unique
158 /// dependence tag number (FP or int).
159 void printIntReg(std::ostream &os, RegIndex reg_idx) const;
160 void printFloatReg(std::ostream &os, RegIndex reg_idx) const;
161 void printVecReg(std::ostream &os, RegIndex reg_idx) const;
162 void printCCReg(std::ostream &os, RegIndex reg_idx) const;
163 void printMiscReg(std::ostream &os, RegIndex reg_idx) const;
164 void printMnemonic(std::ostream &os,
165 const std::string &suffix = "",
166 bool withPred = true,
167 bool withCond64 = false,
168 ConditionCode cond64 = COND_UC) const;
169 void printTarget(std::ostream &os, Addr target,
170 const SymbolTable *symtab) const;
171 void printCondition(std::ostream &os, unsigned code,
172 bool noImplicit=false) const;
173 void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
174 const std::string &prefix, const Addr addr,
175 const std::string &suffix) const;
176 void printShiftOperand(std::ostream &os, IntRegIndex rm,
177 bool immShift, uint32_t shiftAmt,
178 IntRegIndex rs, ArmShiftType type) const;
179 void printExtendOperand(bool firstOperand, std::ostream &os,
180 IntRegIndex rm, ArmExtendType type,
181 int64_t shiftAmt) const;
182
183
184 void printDataInst(std::ostream &os, bool withImm) const;
185 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
186 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
187 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
188 uint64_t imm) const;
189
190 void
191 advancePC(PCState &pcState) const
192 {
193 pcState.advance();
194 }
195
196 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
197
198 static inline uint32_t
199 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,
200 uint8_t byteMask, bool affectState, bool nmfi, ThreadContext *tc)
201 {
202 bool privileged = (cpsr.mode != MODE_USER);
203 bool haveVirt = ArmSystem::haveVirtualization(tc);
204 bool haveSecurity = ArmSystem::haveSecurity(tc);
205 bool isSecure = inSecureState(scr, cpsr) || !haveSecurity;
206
207 uint32_t bitMask = 0;
208
209 if (bits(byteMask, 3)) {
210 unsigned lowIdx = affectState ? 24 : 27;
211 bitMask = bitMask | mask(31, lowIdx);
212 }
213 if (bits(byteMask, 2)) {
214 bitMask = bitMask | mask(19, 16);
215 }
216 if (bits(byteMask, 1)) {
217 unsigned highIdx = affectState ? 15 : 9;
218 unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt))
219 ? 8 : 9;
220 bitMask = bitMask | mask(highIdx, lowIdx);
221 }
222 if (bits(byteMask, 0)) {
223 if (privileged) {
224 bitMask |= 1 << 7;
225 if ( (!nmfi || !((val >> 6) & 0x1)) &&
226 (isSecure || scr.fw || haveVirt) ) {
227 bitMask |= 1 << 6;
228 }
229 // Now check the new mode is allowed
230 OperatingMode newMode = (OperatingMode) (val & mask(5));
231 OperatingMode oldMode = (OperatingMode)(uint32_t)cpsr.mode;
232 if (!badMode(newMode)) {
233 bool validModeChange = true;
234 // Check for attempts to enter modes only permitted in
235 // Secure state from Non-secure state. These are Monitor
236 // mode ('10110'), and FIQ mode ('10001') if the Security
237 // Extensions have reserved it.
238 if (!isSecure && newMode == MODE_MON)
239 validModeChange = false;
240 if (!isSecure && newMode == MODE_FIQ && nsacr.rfr == '1')
241 validModeChange = false;
242 // There is no Hyp mode ('11010') in Secure state, so that
243 // is UNPREDICTABLE
244 if (scr.ns == '0' && newMode == MODE_HYP)
245 validModeChange = false;
246 // Cannot move into Hyp mode directly from a Non-secure
247 // PL1 mode
248 if (!isSecure && oldMode != MODE_HYP && newMode == MODE_HYP)
249 validModeChange = false;
250 // Cannot move out of Hyp mode with this function except
251 // on an exception return
252 if (oldMode == MODE_HYP && newMode != MODE_HYP && !affectState)
253 validModeChange = false;
254 // Must not change to 64 bit when running in 32 bit mode
255 if (!opModeIs64(oldMode) && opModeIs64(newMode))
256 validModeChange = false;
257
258 // If we passed all of the above then set the bit mask to
259 // copy the mode accross
260 if (validModeChange) {
261 bitMask = bitMask | mask(5);
262 } else {
263 warn_once("Illegal change to CPSR mode attempted\n");
264 }
265 } else {
266 warn_once("Ignoring write of bad mode to CPSR.\n");
267 }
268 }
269 if (affectState)
270 bitMask = bitMask | (1 << 5);
271 }
272
273 return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
274 }
275
276 static inline uint32_t
277 spsrWriteByInstr(uint32_t spsr, uint32_t val,
278 uint8_t byteMask, bool affectState)
279 {
280 uint32_t bitMask = 0;
281
282 if (bits(byteMask, 3))
283 bitMask = bitMask | mask(31, 24);
284 if (bits(byteMask, 2))
285 bitMask = bitMask | mask(19, 16);
286 if (bits(byteMask, 1))
287 bitMask = bitMask | mask(15, 8);
288 if (bits(byteMask, 0))
289 bitMask = bitMask | mask(7, 0);
290
291 return ((spsr & ~bitMask) | (val & bitMask));
292 }
293
|