1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 28 unchanged lines hidden (view full) ---

39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "arch/arm/faults.hh"
46#include "arch/arm/utility.hh"
47#include "base/trace.hh"
48#include "cpu/static_inst.hh"
49#include "sim/byteswap.hh"
50#include "sim/full_system.hh"
51
52namespace ArmISA
53{
54
55class ArmStaticInst : public StaticInst
56{
57 protected:
58 int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
59 uint32_t type, uint32_t cfval) const;
60 int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
61 uint32_t type, uint32_t cfval) const;
62
63 bool shift_carry_imm(uint32_t base, uint32_t shamt,
64 uint32_t type, uint32_t cfval) const;
65 bool shift_carry_rs(uint32_t base, uint32_t shamt,
66 uint32_t type, uint32_t cfval) const;
67
68 template<int width>
69 static inline bool
70 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
71 {
72 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
73 if (bits(midRes, width) != bits(midRes, width - 1)) {
74 if (midRes > 0)
75 res = (LL(1) << (width - 1)) - 1;

--- 54 unchanged lines hidden (view full) ---

130 }
131 }
132
133 // Constructor
134 ArmStaticInst(const char *mnem, ExtMachInst _machInst,
135 OpClass __opClass)
136 : StaticInst(mnem, _machInst, __opClass)
137 {
138 }
139
140 /// Print a register name for disassembly given the unique
141 /// dependence tag number (FP or int).
142 void printReg(std::ostream &os, int reg) const;
143 void printMnemonic(std::ostream &os,
144 const std::string &suffix = "",
145 bool withPred = true) const;
146 void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
147 const std::string &prefix, const Addr addr,
148 const std::string &suffix) const;
149 void printShiftOperand(std::ostream &os, IntRegIndex rm,
150 bool immShift, uint32_t shiftAmt,
151 IntRegIndex rs, ArmShiftType type) const;
152
153
154 void printDataInst(std::ostream &os, bool withImm) const;
155 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
156 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
157 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
158 uint32_t imm) const;
159
160 void
161 advancePC(PCState &pcState) const
162 {
163 pcState.advance();
164 }
165
166 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
167
168 static inline uint32_t
169 cpsrWriteByInstr(CPSR cpsr, uint32_t val,
170 uint8_t byteMask, bool affectState, bool nmfi)
171 {
172 bool privileged = (cpsr.mode != MODE_USER);
173
174 uint32_t bitMask = 0;
175
176 if (bits(byteMask, 3)) {
177 unsigned lowIdx = affectState ? 24 : 27;
178 bitMask = bitMask | mask(31, lowIdx);
179 }
180 if (bits(byteMask, 2)) {
181 bitMask = bitMask | mask(19, 16);
182 }
183 if (bits(byteMask, 1)) {
184 unsigned highIdx = affectState ? 15 : 9;
185 unsigned lowIdx = privileged ? 8 : 9;
186 bitMask = bitMask | mask(highIdx, lowIdx);
187 }
188 if (bits(byteMask, 0)) {
189 if (privileged) {
190 bitMask = bitMask | mask(7, 6);
191 if (!badMode((OperatingMode)(val & mask(5)))) {
192 bitMask = bitMask | mask(5);
193 } else {
194 warn_once("Ignoring write of bad mode to CPSR.\n");
195 }
196 }
197 if (affectState)
198 bitMask = bitMask | (1 << 5);
199 }
200
201 bool cpsr_f = cpsr.f;
202 uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
203 if (nmfi && !cpsr_f)
204 new_cpsr &= ~(1 << 6);
205 return new_cpsr;
206 }
207
208 static inline uint32_t
209 spsrWriteByInstr(uint32_t spsr, uint32_t val,
210 uint8_t byteMask, bool affectState)
211 {
212 uint32_t bitMask = 0;
213

--- 77 unchanged lines hidden (view full) ---

291 PCState pc = xc->pcState();
292 pc.instAIWNPC(val);
293 xc->pcState(pc);
294 }
295
296 inline Fault
297 disabledFault() const
298 {
299 if (FullSystem) {
300 return new UndefinedInstruction();
301 } else {
302 return new UndefinedInstruction(machInst, false, mnemonic, true);
303 }
304 }
305};
306}
307
308#endif //__ARCH_ARM_INSTS_STATICINST_HH__