1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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150
151
152 void printDataInst(std::ostream &os, bool withImm) const;
153 void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
154 IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
155 IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
156 uint32_t imm) const;
157
158 void
159 advancePC(PCState &pcState) const
160 {
161 pcState.advance();
162 }
163
164 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
165
166 static inline uint32_t
167 cpsrWriteByInstr(CPSR cpsr, uint32_t val,
168 uint8_t byteMask, bool affectState, bool nmfi)
169 {
170 bool privileged = (cpsr.mode != MODE_USER);
171

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220
221 return ((spsr & ~bitMask) | (val & bitMask));
222 }
223
224 template<class XC>
225 static inline Addr
226 readPC(XC *xc)
227 {
228 return xc->pcState().instPC();
229 }
230
231 template<class XC>
232 static inline void
233 setNextPC(XC *xc, Addr val)
234 {
235 PCState pc = xc->pcState();
236 pc.instNPC(val);
237 xc->pcState(pc);
238 }
239
240 template<class T>
241 static inline T
242 cSwap(T val, bool big)
243 {
244 if (big) {
245 return gtobe(val);

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270 return gtoh(conv.tVal);
271 }
272
273 // Perform an interworking branch.
274 template<class XC>
275 static inline void
276 setIWNextPC(XC *xc, Addr val)
277 {
278 PCState pc = xc->pcState();
279 pc.instIWNPC(val);
280 xc->pcState(pc);
281 }
282
283 // Perform an interworking branch in ARM mode, a regular branch
284 // otherwise.
285 template<class XC>
286 static inline void
287 setAIWNextPC(XC *xc, Addr val)
288 {
289 PCState pc = xc->pcState();
290 pc.instAIWNPC(val);
291 xc->pcState(pc);
292 }
293
294 inline Fault
295 disabledFault() const
296 {
297#if FULL_SYSTEM
298 return new UndefinedInstruction();
299#else
300 return new UndefinedInstruction(machInst, false, mnemonic, true);
301#endif
302 }
303};
304}
305
306#endif //__ARCH_ARM_INSTS_STATICINST_HH__