1/*
2 * Copyright (c) 2010-2013, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include <memory>
46
47#include "arch/arm/faults.hh"
48#include "arch/arm/utility.hh"
49#include "arch/arm/system.hh"
50#include "base/trace.hh"
51#include "cpu/exec_context.hh"
52#include "cpu/static_inst.hh"
53#include "sim/byteswap.hh"
54#include "sim/full_system.hh"
55
56namespace ArmISA
57{
58
59class ArmStaticInst : public StaticInst

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286 if (bits(byteMask, 1))
287 bitMask = bitMask | mask(15, 8);
288 if (bits(byteMask, 0))
289 bitMask = bitMask | mask(7, 0);
290
291 return ((spsr & ~bitMask) | (val & bitMask));
292 }
293
294 static inline Addr
295 readPC(ExecContext *xc)
296 {
297 return xc->pcState().instPC();
298 }
299
300 static inline void
301 setNextPC(ExecContext *xc, Addr val)
302 {
303 PCState pc = xc->pcState();
304 pc.instNPC(val);
305 xc->pcState(pc);
306 }
307
308 template<class T>
309 static inline T

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334 for (unsigned i = 0; i < count; i++) {
335 conv.eVals[i] = gtole(conv.eVals[i]);
336 }
337 }
338 return gtoh(conv.tVal);
339 }
340
341 // Perform an interworking branch.
342 static inline void
343 setIWNextPC(ExecContext *xc, Addr val)
344 {
345 PCState pc = xc->pcState();
346 pc.instIWNPC(val);
347 xc->pcState(pc);
348 }
349
350 // Perform an interworking branch in ARM mode, a regular branch
351 // otherwise.
352 static inline void
353 setAIWNextPC(ExecContext *xc, Addr val)
354 {
355 PCState pc = xc->pcState();
356 pc.instAIWNPC(val);
357 xc->pcState(pc);
358 }
359
360 inline Fault
361 disabledFault() const

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