static_inst.cc (9920:028e4da64b42) static_inst.cc (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010-2013 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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81 default:
82 ccprintf(std::cerr, "Unhandled shift type\n");
83 exit(1);
84 break;
85 }
86 return 0;
87}
88
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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81 default:
82 ccprintf(std::cerr, "Unhandled shift type\n");
83 exit(1);
84 break;
85 }
86 return 0;
87}
88
89int64_t
90ArmStaticInst::shiftReg64(uint64_t base, uint64_t shiftAmt,
91 ArmShiftType type, uint8_t width) const
92{
93 shiftAmt = shiftAmt % width;
94 ArmShiftType shiftType;
95 shiftType = (ArmShiftType)type;
96
97 switch (shiftType)
98 {
99 case LSL:
100 return base << shiftAmt;
101 case LSR:
102 if (shiftAmt == 0)
103 return base;
104 else
105 return (base & mask(width)) >> shiftAmt;
106 case ASR:
107 if (shiftAmt == 0) {
108 return base;
109 } else {
110 int sign_bit = bits(base, intWidth - 1);
111 base >>= shiftAmt;
112 base = sign_bit ? (base | ~mask(intWidth - shiftAmt)) : base;
113 return base & mask(intWidth);
114 }
115 case ROR:
116 if (shiftAmt == 0)
117 return base;
118 else
119 return (base << (width - shiftAmt)) | (base >> shiftAmt);
120 default:
121 ccprintf(std::cerr, "Unhandled shift type\n");
122 exit(1);
123 break;
124 }
125 return 0;
126}
127
128int64_t
129ArmStaticInst::extendReg64(uint64_t base, ArmExtendType type,
130 uint64_t shiftAmt, uint8_t width) const
131{
132 bool sign_extend = false;
133 int len = 0;
134 switch (type) {
135 case UXTB:
136 len = 8;
137 break;
138 case UXTH:
139 len = 16;
140 break;
141 case UXTW:
142 len = 32;
143 break;
144 case UXTX:
145 len = 64;
146 break;
147 case SXTB:
148 len = 8;
149 sign_extend = true;
150 break;
151 case SXTH:
152 len = 16;
153 sign_extend = true;
154 break;
155 case SXTW:
156 len = 32;
157 sign_extend = true;
158 break;
159 case SXTX:
160 len = 64;
161 sign_extend = true;
162 break;
163 }
164 len = len <= width - shiftAmt ? len : width - shiftAmt;
165 uint64_t tmp = (uint64_t) bits(base, len - 1, 0) << shiftAmt;
166 if (sign_extend) {
167 int sign_bit = bits(tmp, len + shiftAmt - 1);
168 tmp = sign_bit ? (tmp | ~mask(len + shiftAmt)) : tmp;
169 }
170 return tmp & mask(width);
171}
172
89// Shift Rm by Rs
90int32_t
91ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
92 uint32_t type, uint32_t cfval) const
93{
94 enum ArmShiftType shiftType;
95 shiftType = (enum ArmShiftType) type;
96

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209
210void
211ArmStaticInst::printReg(std::ostream &os, int reg) const
212{
213 RegIndex rel_reg;
214
215 switch (regIdxToClass(reg, &rel_reg)) {
216 case IntRegClass:
173// Shift Rm by Rs
174int32_t
175ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
176 uint32_t type, uint32_t cfval) const
177{
178 enum ArmShiftType shiftType;
179 shiftType = (enum ArmShiftType) type;
180

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293
294void
295ArmStaticInst::printReg(std::ostream &os, int reg) const
296{
297 RegIndex rel_reg;
298
299 switch (regIdxToClass(reg, &rel_reg)) {
300 case IntRegClass:
217 switch (rel_reg) {
218 case PCReg:
219 ccprintf(os, "pc");
220 break;
221 case StackPointerReg:
222 ccprintf(os, "sp");
223 break;
224 case FramePointerReg:
225 ccprintf(os, "fp");
226 break;
227 case ReturnAddressReg:
228 ccprintf(os, "lr");
229 break;
230 default:
231 ccprintf(os, "r%d", reg);
232 break;
301 if (aarch64) {
302 if (reg == INTREG_UREG0)
303 ccprintf(os, "ureg0");
304 else if (reg == INTREG_SPX)
305 ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
306 else if (reg == INTREG_X31)
307 ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
308 else
309 ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg);
310 } else {
311 switch (rel_reg) {
312 case PCReg:
313 ccprintf(os, "pc");
314 break;
315 case StackPointerReg:
316 ccprintf(os, "sp");
317 break;
318 case FramePointerReg:
319 ccprintf(os, "fp");
320 break;
321 case ReturnAddressReg:
322 ccprintf(os, "lr");
323 break;
324 default:
325 ccprintf(os, "r%d", reg);
326 break;
327 }
233 }
234 break;
235 case FloatRegClass:
236 ccprintf(os, "f%d", rel_reg);
237 break;
238 case MiscRegClass:
239 assert(rel_reg < NUM_MISCREGS);
240 ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
241 break;
242 case CCRegClass:
243 panic("printReg: CCRegClass but ARM has no CC regs\n");
244 }
245}
246
247void
248ArmStaticInst::printMnemonic(std::ostream &os,
249 const std::string &suffix,
328 }
329 break;
330 case FloatRegClass:
331 ccprintf(os, "f%d", rel_reg);
332 break;
333 case MiscRegClass:
334 assert(rel_reg < NUM_MISCREGS);
335 ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
336 break;
337 case CCRegClass:
338 panic("printReg: CCRegClass but ARM has no CC regs\n");
339 }
340}
341
342void
343ArmStaticInst::printMnemonic(std::ostream &os,
344 const std::string &suffix,
250 bool withPred) const
345 bool withPred,
346 bool withCond64,
347 ConditionCode cond64) const
251{
252 os << " " << mnemonic;
348{
349 os << " " << mnemonic;
253 if (withPred) {
254 unsigned condCode = machInst.condCode;
255 switch (condCode) {
256 case COND_EQ:
257 os << "eq";
258 break;
259 case COND_NE:
260 os << "ne";
261 break;
262 case COND_CS:
263 os << "cs";
264 break;
265 case COND_CC:
266 os << "cc";
267 break;
268 case COND_MI:
269 os << "mi";
270 break;
271 case COND_PL:
272 os << "pl";
273 break;
274 case COND_VS:
275 os << "vs";
276 break;
277 case COND_VC:
278 os << "vc";
279 break;
280 case COND_HI:
281 os << "hi";
282 break;
283 case COND_LS:
284 os << "ls";
285 break;
286 case COND_GE:
287 os << "ge";
288 break;
289 case COND_LT:
290 os << "lt";
291 break;
292 case COND_GT:
293 os << "gt";
294 break;
295 case COND_LE:
296 os << "le";
297 break;
298 case COND_AL:
299 // This one is implicit.
300 break;
301 case COND_UC:
302 // Unconditional.
303 break;
304 default:
305 panic("Unrecognized condition code %d.\n", condCode);
306 }
350 if (withPred && !aarch64) {
351 printCondition(os, machInst.condCode);
307 os << suffix;
352 os << suffix;
308 if (machInst.bigThumb)
309 os << ".w";
310 os << " ";
353 } else if (withCond64) {
354 os << ".";
355 printCondition(os, cond64);
356 os << suffix;
311 }
357 }
358 if (machInst.bigThumb)
359 os << ".w";
360 os << " ";
312}
313
314void
361}
362
363void
364ArmStaticInst::printTarget(std::ostream &os, Addr target,
365 const SymbolTable *symtab) const
366{
367 Addr symbolAddr;
368 std::string symbol;
369
370 if (symtab && symtab->findNearestSymbol(target, symbol, symbolAddr)) {
371 ccprintf(os, "<%s", symbol);
372 if (symbolAddr != target)
373 ccprintf(os, "+%d>", target - symbolAddr);
374 else
375 ccprintf(os, ">");
376 } else {
377 ccprintf(os, "%#x", target);
378 }
379}
380
381void
382ArmStaticInst::printCondition(std::ostream &os,
383 unsigned code,
384 bool noImplicit) const
385{
386 switch (code) {
387 case COND_EQ:
388 os << "eq";
389 break;
390 case COND_NE:
391 os << "ne";
392 break;
393 case COND_CS:
394 os << "cs";
395 break;
396 case COND_CC:
397 os << "cc";
398 break;
399 case COND_MI:
400 os << "mi";
401 break;
402 case COND_PL:
403 os << "pl";
404 break;
405 case COND_VS:
406 os << "vs";
407 break;
408 case COND_VC:
409 os << "vc";
410 break;
411 case COND_HI:
412 os << "hi";
413 break;
414 case COND_LS:
415 os << "ls";
416 break;
417 case COND_GE:
418 os << "ge";
419 break;
420 case COND_LT:
421 os << "lt";
422 break;
423 case COND_GT:
424 os << "gt";
425 break;
426 case COND_LE:
427 os << "le";
428 break;
429 case COND_AL:
430 // This one is implicit.
431 if (noImplicit)
432 os << "al";
433 break;
434 case COND_UC:
435 // Unconditional.
436 if (noImplicit)
437 os << "uc";
438 break;
439 default:
440 panic("Unrecognized condition code %d.\n", code);
441 }
442}
443
444void
315ArmStaticInst::printMemSymbol(std::ostream &os,
316 const SymbolTable *symtab,
317 const std::string &prefix,
318 const Addr addr,
319 const std::string &suffix) const
320{
321 Addr symbolAddr;
322 std::string symbol;

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388 if (immShift)
389 os << "#" << shiftAmt;
390 else
391 printReg(os, rs);
392 }
393}
394
395void
445ArmStaticInst::printMemSymbol(std::ostream &os,
446 const SymbolTable *symtab,
447 const std::string &prefix,
448 const Addr addr,
449 const std::string &suffix) const
450{
451 Addr symbolAddr;
452 std::string symbol;

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518 if (immShift)
519 os << "#" << shiftAmt;
520 else
521 printReg(os, rs);
522 }
523}
524
525void
526ArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os,
527 IntRegIndex rm, ArmExtendType type,
528 int64_t shiftAmt) const
529{
530 if (!firstOperand)
531 ccprintf(os, ", ");
532 printReg(os, rm);
533 if (type == UXTX && shiftAmt == 0)
534 return;
535 switch (type) {
536 case UXTB: ccprintf(os, ", UXTB");
537 break;
538 case UXTH: ccprintf(os, ", UXTH");
539 break;
540 case UXTW: ccprintf(os, ", UXTW");
541 break;
542 case UXTX: ccprintf(os, ", LSL");
543 break;
544 case SXTB: ccprintf(os, ", SXTB");
545 break;
546 case SXTH: ccprintf(os, ", SXTH");
547 break;
548 case SXTW: ccprintf(os, ", SXTW");
549 break;
550 case SXTX: ccprintf(os, ", SXTW");
551 break;
552 }
553 if (type == UXTX || shiftAmt)
554 ccprintf(os, " #%d", shiftAmt);
555}
556
557void
396ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
397 bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
398 IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
399 ArmShiftType type, uint32_t imm) const
400{
401 printMnemonic(os, s ? "s" : "");
402 bool firstOp = true;
403

--- 32 unchanged lines hidden --- 		558ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
559 bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
560 IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
561 ArmShiftType type, uint32_t imm) const
562{
563 printMnemonic(os, s ? "s" : "");
564 bool firstOp = true;
565

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