static_inst.cc (8229:78bf55f23338) static_inst.cc (9913:7f43babfde6a)
1/*
2 * Copyright (c) 2010 ARM Limited
1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/static_inst.hh"
44#include "arch/arm/faults.hh"
45#include "base/loader/symtab.hh"
46#include "base/condcodes.hh"
47#include "base/cprintf.hh"
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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41 * Authors: Stephen Hines
42 */
43
44#include "arch/arm/insts/static_inst.hh"
45#include "arch/arm/faults.hh"
46#include "base/loader/symtab.hh"
47#include "base/condcodes.hh"
48#include "base/cprintf.hh"
49#include "cpu/reg_class.hh"
48
49namespace ArmISA
50{
51// Shift Rm by an immediate value
52int32_t
53ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
54 uint32_t type, uint32_t cfval) const
55{

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203 }
204 return 0;
205}
206
207
208void
209ArmStaticInst::printReg(std::ostream &os, int reg) const
210{
50
51namespace ArmISA
52{
53// Shift Rm by an immediate value
54int32_t
55ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
56 uint32_t type, uint32_t cfval) const
57{

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205 }
206 return 0;
207}
208
209
210void
211ArmStaticInst::printReg(std::ostream &os, int reg) const
212{
211 if (reg < FP_Base_DepTag) {
212 switch (reg) {
213 RegIndex rel_reg;
214
215 switch (regIdxToClass(reg, &rel_reg)) {
216 case IntRegClass:
217 switch (rel_reg) {
213 case PCReg:
214 ccprintf(os, "pc");
215 break;
216 case StackPointerReg:
217 ccprintf(os, "sp");
218 break;
219 case FramePointerReg:
220 ccprintf(os, "fp");
221 break;
222 case ReturnAddressReg:
223 ccprintf(os, "lr");
224 break;
225 default:
226 ccprintf(os, "r%d", reg);
227 break;
228 }
218 case PCReg:
219 ccprintf(os, "pc");
220 break;
221 case StackPointerReg:
222 ccprintf(os, "sp");
223 break;
224 case FramePointerReg:
225 ccprintf(os, "fp");
226 break;
227 case ReturnAddressReg:
228 ccprintf(os, "lr");
229 break;
230 default:
231 ccprintf(os, "r%d", reg);
232 break;
233 }
229 } else if (reg < Ctrl_Base_DepTag) {
230 ccprintf(os, "f%d", reg - FP_Base_DepTag);
231 } else {
232 reg -= Ctrl_Base_DepTag;
233 assert(reg < NUM_MISCREGS);
234 ccprintf(os, "%s", ArmISA::miscRegName[reg]);
234 break;
235 case FloatRegClass:
236 ccprintf(os, "f%d", rel_reg);
237 break;
238 case MiscRegClass:
239 assert(rel_reg < NUM_MISCREGS);
240 ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
241 break;
235 }
236}
237
238void
239ArmStaticInst::printMnemonic(std::ostream &os,
240 const std::string &suffix,
241 bool withPred) const
242{

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243}
244
245void
246ArmStaticInst::printMnemonic(std::ostream &os,
247 const std::string &suffix,
248 bool withPred) const
249{

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