static_inst.cc (7145:a71ac505d83b) static_inst.cc (7148:1f8d18f5fe5d)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45#include "base/condcodes.hh"
46#include "base/cprintf.hh"
47#include "base/loader/symtab.hh"
48
49namespace ArmISA
50{
51// Shift Rm by an immediate value
52int32_t
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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45#include "base/condcodes.hh"
46#include "base/cprintf.hh"
47#include "base/loader/symtab.hh"
48
49namespace ArmISA
50{
51// Shift Rm by an immediate value
52int32_t
53ArmStaticInstBase::shift_rm_imm(uint32_t base, uint32_t shamt,
53ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
54 uint32_t type, uint32_t cfval) const
55{
56 assert(shamt < 32);
57 ArmShiftType shiftType;
58 shiftType = (ArmShiftType)type;
59
60 switch (shiftType)
61 {

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81 exit(1);
82 break;
83 }
84 return 0;
85}
86
87// Shift Rm by Rs
88int32_t
54 uint32_t type, uint32_t cfval) const
55{
56 assert(shamt < 32);
57 ArmShiftType shiftType;
58 shiftType = (ArmShiftType)type;
59
60 switch (shiftType)
61 {

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81 exit(1);
82 break;
83 }
84 return 0;
85}
86
87// Shift Rm by Rs
88int32_t
89ArmStaticInstBase::shift_rm_rs(uint32_t base, uint32_t shamt,
89ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
90 uint32_t type, uint32_t cfval) const
91{
92 enum ArmShiftType shiftType;
93 shiftType = (enum ArmShiftType) type;
94
95 switch (shiftType)
96 {
97 case LSL:

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121 break;
122 }
123 return 0;
124}
125
126
127// Generate C for a shift by immediate
128bool
90 uint32_t type, uint32_t cfval) const
91{
92 enum ArmShiftType shiftType;
93 shiftType = (enum ArmShiftType) type;
94
95 switch (shiftType)
96 {
97 case LSL:

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121 break;
122 }
123 return 0;
124}
125
126
127// Generate C for a shift by immediate
128bool
129ArmStaticInstBase::shift_carry_imm(uint32_t base, uint32_t shamt,
129ArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt,
130 uint32_t type, uint32_t cfval) const
131{
132 enum ArmShiftType shiftType;
133 shiftType = (enum ArmShiftType) type;
134
135 switch (shiftType)
136 {
137 case LSL:

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161 break;
162 }
163 return 0;
164}
165
166
167// Generate C for a shift by Rs
168bool
130 uint32_t type, uint32_t cfval) const
131{
132 enum ArmShiftType shiftType;
133 shiftType = (enum ArmShiftType) type;
134
135 switch (shiftType)
136 {
137 case LSL:

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161 break;
162 }
163 return 0;
164}
165
166
167// Generate C for a shift by Rs
168bool
169ArmStaticInstBase::shift_carry_rs(uint32_t base, uint32_t shamt,
169ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
170 uint32_t type, uint32_t cfval) const
171{
172 enum ArmShiftType shiftType;
173 shiftType = (enum ArmShiftType) type;
174
175 if (shamt == 0)
176 return cfval;
177

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201 exit(1);
202 break;
203 }
204 return 0;
205}
206
207
208void
170 uint32_t type, uint32_t cfval) const
171{
172 enum ArmShiftType shiftType;
173 shiftType = (enum ArmShiftType) type;
174
175 if (shamt == 0)
176 return cfval;
177

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201 exit(1);
202 break;
203 }
204 return 0;
205}
206
207
208void
209ArmStaticInstBase::printReg(std::ostream &os, int reg) const
209ArmStaticInst::printReg(std::ostream &os, int reg) const
210{
211 if (reg < FP_Base_DepTag) {
212 switch (reg) {
213 case PCReg:
214 ccprintf(os, "pc");
215 break;
216 case StackPointerReg:
217 ccprintf(os, "sp");

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231 } else {
232 reg -= Ctrl_Base_DepTag;
233 assert(reg < NUM_MISCREGS);
234 ccprintf(os, "%s", ArmISA::miscRegName[reg]);
235 }
236}
237
238void
210{
211 if (reg < FP_Base_DepTag) {
212 switch (reg) {
213 case PCReg:
214 ccprintf(os, "pc");
215 break;
216 case StackPointerReg:
217 ccprintf(os, "sp");

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231 } else {
232 reg -= Ctrl_Base_DepTag;
233 assert(reg < NUM_MISCREGS);
234 ccprintf(os, "%s", ArmISA::miscRegName[reg]);
235 }
236}
237
238void
239ArmStaticInstBase::printMnemonic(std::ostream &os,
239ArmStaticInst::printMnemonic(std::ostream &os,
240 const std::string &suffix,
241 bool withPred) const
242{
243 os << " " << mnemonic;
244 if (withPred) {
245 unsigned condCode = machInst.condCode;
246 switch (condCode) {
247 case COND_EQ:

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298 os << suffix;
299 if (machInst.bigThumb)
300 os << ".w";
301 os << " ";
302 }
303}
304
305void
240 const std::string &suffix,
241 bool withPred) const
242{
243 os << " " << mnemonic;
244 if (withPred) {
245 unsigned condCode = machInst.condCode;
246 switch (condCode) {
247 case COND_EQ:

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298 os << suffix;
299 if (machInst.bigThumb)
300 os << ".w";
301 os << " ";
302 }
303}
304
305void
306ArmStaticInstBase::printMemSymbol(std::ostream &os,
306ArmStaticInst::printMemSymbol(std::ostream &os,
307 const SymbolTable *symtab,
308 const std::string &prefix,
309 const Addr addr,
310 const std::string &suffix) const
311{
312 Addr symbolAddr;
313 std::string symbol;
314 if (symtab && symtab->findNearestSymbol(addr, symbol, symbolAddr)) {
315 ccprintf(os, "%s%s", prefix, symbol);
316 if (symbolAddr != addr)
317 ccprintf(os, "+%d", addr - symbolAddr);
318 ccprintf(os, suffix);
319 }
320}
321
322void
307 const SymbolTable *symtab,
308 const std::string &prefix,
309 const Addr addr,
310 const std::string &suffix) const
311{
312 Addr symbolAddr;
313 std::string symbol;
314 if (symtab && symtab->findNearestSymbol(addr, symbol, symbolAddr)) {
315 ccprintf(os, "%s%s", prefix, symbol);
316 if (symbolAddr != addr)
317 ccprintf(os, "+%d", addr - symbolAddr);
318 ccprintf(os, suffix);
319 }
320}
321
322void
323ArmStaticInstBase::printShiftOperand(std::ostream &os,
323ArmStaticInst::printShiftOperand(std::ostream &os,
324 IntRegIndex rm,
325 bool immShift,
326 uint32_t shiftAmt,
327 IntRegIndex rs,
328 ArmShiftType type) const
329{
330 bool firstOp = false;
331

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379 if (immShift)
380 os << "#" << shiftAmt;
381 else
382 printReg(os, rs);
383 }
384}
385
386void
324 IntRegIndex rm,
325 bool immShift,
326 uint32_t shiftAmt,
327 IntRegIndex rs,
328 ArmShiftType type) const
329{
330 bool firstOp = false;
331

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379 if (immShift)
380 os << "#" << shiftAmt;
381 else
382 printReg(os, rs);
383 }
384}
385
386void
387ArmStaticInstBase::printDataInst(std::ostream &os, bool withImm,
387ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
388 bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
389 IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
390 ArmShiftType type, uint32_t imm) const
391{
392 printMnemonic(os, s ? "s" : "");
393 bool firstOp = true;
394
395 // Destination

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411 if (withImm) {
412 ccprintf(os, "#%d", imm);
413 } else {
414 printShiftOperand(os, rm, immShift, shiftAmt, rs, type);
415 }
416}
417
418std::string
388 bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
389 IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
390 ArmShiftType type, uint32_t imm) const
391{
392 printMnemonic(os, s ? "s" : "");
393 bool firstOp = true;
394
395 // Destination

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411 if (withImm) {
412 ccprintf(os, "#%d", imm);
413 } else {
414 printShiftOperand(os, rm, immShift, shiftAmt, rs, type);
415 }
416}
417
418std::string
419ArmStaticInstBase::generateDisassembly(Addr pc,
419ArmStaticInst::generateDisassembly(Addr pc,
420 const SymbolTable *symtab) const
421{
422 std::stringstream ss;
423 printMnemonic(ss);
424 return ss.str();
425}
426}
420 const SymbolTable *symtab) const
421{
422 std::stringstream ss;
423 printMnemonic(ss);
424 return ss.str();
425}
426}