static_inst.cc (7140:d2f0418e9390) static_inst.cc (7142:c63c06703d0f)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 332 unchanged lines hidden (view full) ---

341 ccprintf(os, "%s%s", prefix, symbol);
342 if (symbolAddr != addr)
343 ccprintf(os, "+%d", addr - symbolAddr);
344 ccprintf(os, suffix);
345 }
346}
347
348void
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 332 unchanged lines hidden (view full) ---

341 ccprintf(os, "%s%s", prefix, symbol);
342 if (symbolAddr != addr)
343 ccprintf(os, "+%d", addr - symbolAddr);
344 ccprintf(os, suffix);
345 }
346}
347
348void
349ArmStaticInstBase::printShiftOperand(std::ostream &os) const
349ArmStaticInstBase::printShiftOperand(std::ostream &os,
350 IntRegIndex rm,
351 bool immShift,
352 uint32_t shiftAmt,
353 IntRegIndex rs,
354 ArmShiftType type) const
350{
355{
351 printReg(os, machInst.rm);
356 bool firstOp = false;
352
357
353 bool immShift = (machInst.opcode4 == 0);
358 if (rm != INTREG_ZERO) {
359 printReg(os, rm);
360 }
361
354 bool done = false;
362 bool done = false;
355 unsigned shiftAmt = (machInst.shiftSize);
356 ArmShiftType type = (ArmShiftType)(uint32_t)machInst.shift;
357
358 if ((type == LSR || type == ASR) && immShift && shiftAmt == 0)
359 shiftAmt = 32;
360
361 switch (type) {
362 case LSL:
363 if (immShift && shiftAmt == 0) {
364 done = true;
365 break;
366 }
363
364 if ((type == LSR || type == ASR) && immShift && shiftAmt == 0)
365 shiftAmt = 32;
366
367 switch (type) {
368 case LSL:
369 if (immShift && shiftAmt == 0) {
370 done = true;
371 break;
372 }
367 os << ", LSL";
373 if (!firstOp)
374 os << ", ";
375 os << "LSL";
368 break;
369 case LSR:
376 break;
377 case LSR:
370 os << ", LSR";
378 if (!firstOp)
379 os << ", ";
380 os << "LSR";
371 break;
372 case ASR:
381 break;
382 case ASR:
373 os << ", ASR";
383 if (!firstOp)
384 os << ", ";
385 os << "ASR";
374 break;
375 case ROR:
376 if (immShift && shiftAmt == 0) {
386 break;
387 case ROR:
388 if (immShift && shiftAmt == 0) {
377 os << ", RRX";
389 if (!firstOp)
390 os << ", ";
391 os << "RRX";
378 done = true;
379 break;
380 }
392 done = true;
393 break;
394 }
381 os << ", ROR";
395 if (!firstOp)
396 os << ", ";
397 os << "ROR";
382 break;
383 default:
384 panic("Tried to disassemble unrecognized shift type.\n");
385 }
386 if (!done) {
398 break;
399 default:
400 panic("Tried to disassemble unrecognized shift type.\n");
401 }
402 if (!done) {
387 os << " ";
403 if (!firstOp)
404 os << " ";
388 if (immShift)
389 os << "#" << shiftAmt;
390 else
405 if (immShift)
406 os << "#" << shiftAmt;
407 else
391 printReg(os, machInst.rs);
408 printReg(os, rs);
392 }
393}
394
395void
409 }
410}
411
412void
396ArmStaticInstBase::printDataInst(std::ostream &os, bool withImm) const
413ArmStaticInstBase::printDataInst(std::ostream &os, bool withImm,
414 bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
415 IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
416 ArmShiftType type, uint32_t imm) const
397{
417{
398 printMnemonic(os, machInst.sField ? "s" : "");
399 //XXX It would be nice if the decoder figured this all out for us.
400 unsigned opcode = machInst.opcode;
418 printMnemonic(os, s ? "s" : "");
401 bool firstOp = true;
402
403 // Destination
419 bool firstOp = true;
420
421 // Destination
404 // Cmp, cmn, teq, and tst don't have one.
405 if (opcode < 8 || opcode > 0xb) {
422 if (rd != INTREG_ZERO) {
406 firstOp = false;
423 firstOp = false;
407 printReg(os, machInst.rd);
424 printReg(os, rd);
408 }
409
410 // Source 1.
425 }
426
427 // Source 1.
411 // Mov and Movn don't have one of these.
412 if (opcode != 0xd && opcode != 0xf) {
428 if (rn != INTREG_ZERO) {
413 if (!firstOp)
414 os << ", ";
415 firstOp = false;
429 if (!firstOp)
430 os << ", ";
431 firstOp = false;
416 printReg(os, machInst.rn);
432 printReg(os, rn);
417 }
418
419 if (!firstOp)
420 os << ", ";
421 if (withImm) {
433 }
434
435 if (!firstOp)
436 os << ", ";
437 if (withImm) {
422 unsigned rotate = machInst.rotate * 2;
423 uint32_t imm = machInst.imm;
424 ccprintf(os, "#%#x", (imm << (32 - rotate)) | (imm >> rotate));
438 ccprintf(os, "#%d", imm);
425 } else {
439 } else {
426 printShiftOperand(os);
440 printShiftOperand(os, rm, immShift, shiftAmt, rs, type);
427 }
428}
429
430std::string
431ArmStaticInstBase::generateDisassembly(Addr pc,
432 const SymbolTable *symtab) const
433{
434 std::stringstream ss;
435 printMnemonic(ss);
436 return ss.str();
437}
438}
441 }
442}
443
444std::string
445ArmStaticInstBase::generateDisassembly(Addr pc,
446 const SymbolTable *symtab) const
447{
448 std::stringstream ss;
449 printMnemonic(ss);
450 return ss.str();
451}
452}