static_inst.cc (6759:98101a5f7ee4) static_inst.cc (7094:4d878c4a0c2b)
1/* Copyright (c) 2007-2008 The Florida State University
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the

--- 22 unchanged lines hidden (view full) ---

32#include "base/condcodes.hh"
33#include "base/cprintf.hh"
34#include "base/loader/symtab.hh"
35
36namespace ArmISA
37{
38// Shift Rm by an immediate value
39int32_t
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the

--- 22 unchanged lines hidden (view full) ---

45#include "base/condcodes.hh"
46#include "base/cprintf.hh"
47#include "base/loader/symtab.hh"
48
49namespace ArmISA
50{
51// Shift Rm by an immediate value
52int32_t
40ArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt,
41 uint32_t type, uint32_t cfval) const
53ArmStaticInstBase::shift_rm_imm(uint32_t base, uint32_t shamt,
54 uint32_t type, uint32_t cfval) const
42{
43 assert(shamt < 32);
44 ArmShiftType shiftType;
45 shiftType = (ArmShiftType)type;
46
47 switch (shiftType)
48 {
49 case LSL:

--- 18 unchanged lines hidden (view full) ---

68 exit(1);
69 break;
70 }
71 return 0;
72}
73
74// Shift Rm by Rs
75int32_t
55{
56 assert(shamt < 32);
57 ArmShiftType shiftType;
58 shiftType = (ArmShiftType)type;
59
60 switch (shiftType)
61 {
62 case LSL:

--- 18 unchanged lines hidden (view full) ---

81 exit(1);
82 break;
83 }
84 return 0;
85}
86
87// Shift Rm by Rs
88int32_t
76ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
77 uint32_t type, uint32_t cfval) const
89ArmStaticInstBase::shift_rm_rs(uint32_t base, uint32_t shamt,
90 uint32_t type, uint32_t cfval) const
78{
79 enum ArmShiftType shiftType;
80 shiftType = (enum ArmShiftType) type;
81
82 switch (shiftType)
83 {
84 case LSL:
85 if (shamt >= 32)

--- 22 unchanged lines hidden (view full) ---

108 break;
109 }
110 return 0;
111}
112
113
114// Generate C for a shift by immediate
115bool
91{
92 enum ArmShiftType shiftType;
93 shiftType = (enum ArmShiftType) type;
94
95 switch (shiftType)
96 {
97 case LSL:
98 if (shamt >= 32)

--- 22 unchanged lines hidden (view full) ---

121 break;
122 }
123 return 0;
124}
125
126
127// Generate C for a shift by immediate
128bool
116ArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt,
117 uint32_t type, uint32_t cfval) const
129ArmStaticInstBase::shift_carry_imm(uint32_t base, uint32_t shamt,
130 uint32_t type, uint32_t cfval) const
118{
119 enum ArmShiftType shiftType;
120 shiftType = (enum ArmShiftType) type;
121
122 switch (shiftType)
123 {
124 case LSL:
125 if (shamt == 0)

--- 22 unchanged lines hidden (view full) ---

148 break;
149 }
150 return 0;
151}
152
153
154// Generate C for a shift by Rs
155bool
131{
132 enum ArmShiftType shiftType;
133 shiftType = (enum ArmShiftType) type;
134
135 switch (shiftType)
136 {
137 case LSL:
138 if (shamt == 0)

--- 22 unchanged lines hidden (view full) ---

161 break;
162 }
163 return 0;
164}
165
166
167// Generate C for a shift by Rs
168bool
156ArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt,
157 uint32_t type, uint32_t cfval) const
169ArmStaticInstBase::shift_carry_rs(uint32_t base, uint32_t shamt,
170 uint32_t type, uint32_t cfval) const
158{
159 enum ArmShiftType shiftType;
160 shiftType = (enum ArmShiftType) type;
161
162 if (shamt == 0)
163 return cfval;
164
165 switch (shiftType)

--- 23 unchanged lines hidden (view full) ---

189 break;
190 }
191 return 0;
192}
193
194
195// Generate the appropriate carry bit for an addition operation
196bool
171{
172 enum ArmShiftType shiftType;
173 shiftType = (enum ArmShiftType) type;
174
175 if (shamt == 0)
176 return cfval;
177
178 switch (shiftType)

--- 23 unchanged lines hidden (view full) ---

202 break;
203 }
204 return 0;
205}
206
207
208// Generate the appropriate carry bit for an addition operation
209bool
197ArmStaticInst::arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const
210ArmStaticInstBase::arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const
198{
199 return findCarry(32, result, lhs, rhs);
200}
201
202// Generate the appropriate carry bit for a subtraction operation
203bool
211{
212 return findCarry(32, result, lhs, rhs);
213}
214
215// Generate the appropriate carry bit for a subtraction operation
216bool
204ArmStaticInst::arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const
217ArmStaticInstBase::arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const
205{
206 return findCarry(32, result, lhs, ~rhs);
207}
208
209bool
218{
219 return findCarry(32, result, lhs, ~rhs);
220}
221
222bool
210ArmStaticInst::arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const
223ArmStaticInstBase::arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const
211{
212 return findOverflow(32, result, lhs, rhs);
213}
214
215bool
224{
225 return findOverflow(32, result, lhs, rhs);
226}
227
228bool
216ArmStaticInst::arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const
229ArmStaticInstBase::arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const
217{
218 return findOverflow(32, result, lhs, ~rhs);
219}
220
221void
230{
231 return findOverflow(32, result, lhs, ~rhs);
232}
233
234void
222ArmStaticInst::printReg(std::ostream &os, int reg) const
235ArmStaticInstBase::printReg(std::ostream &os, int reg) const
223{
224 if (reg < FP_Base_DepTag) {
225 switch (reg) {
226 case PCReg:
227 ccprintf(os, "pc");
228 break;
229 case StackPointerReg:
230 ccprintf(os, "sp");

--- 13 unchanged lines hidden (view full) ---

244 } else {
245 reg -= Ctrl_Base_DepTag;
246 assert(reg < NUM_MISCREGS);
247 ccprintf(os, "%s", ArmISA::miscRegName[reg]);
248 }
249}
250
251void
236{
237 if (reg < FP_Base_DepTag) {
238 switch (reg) {
239 case PCReg:
240 ccprintf(os, "pc");
241 break;
242 case StackPointerReg:
243 ccprintf(os, "sp");

--- 13 unchanged lines hidden (view full) ---

257 } else {
258 reg -= Ctrl_Base_DepTag;
259 assert(reg < NUM_MISCREGS);
260 ccprintf(os, "%s", ArmISA::miscRegName[reg]);
261 }
262}
263
264void
252ArmStaticInst::printMnemonic(std::ostream &os,
265ArmStaticInstBase::printMnemonic(std::ostream &os,
253 const std::string &suffix,
254 bool withPred) const
255{
256 os << " " << mnemonic;
257 if (withPred) {
258 unsigned condCode = machInst.condCode;
259 switch (condCode) {
260 case COND_EQ:

--- 47 unchanged lines hidden (view full) ---

308 default:
309 panic("Unrecognized condition code %d.\n", condCode);
310 }
311 os << suffix << " ";
312 }
313}
314
315void
266 const std::string &suffix,
267 bool withPred) const
268{
269 os << " " << mnemonic;
270 if (withPred) {
271 unsigned condCode = machInst.condCode;
272 switch (condCode) {
273 case COND_EQ:

--- 47 unchanged lines hidden (view full) ---

321 default:
322 panic("Unrecognized condition code %d.\n", condCode);
323 }
324 os << suffix << " ";
325 }
326}
327
328void
316ArmStaticInst::printMemSymbol(std::ostream &os,
329ArmStaticInstBase::printMemSymbol(std::ostream &os,
317 const SymbolTable *symtab,
318 const std::string &prefix,
319 const Addr addr,
320 const std::string &suffix) const
321{
322 Addr symbolAddr;
323 std::string symbol;
324 if (symtab && symtab->findNearestSymbol(addr, symbol, symbolAddr)) {
325 ccprintf(os, "%s%s", prefix, symbol);
326 if (symbolAddr != addr)
327 ccprintf(os, "+%d", addr - symbolAddr);
328 ccprintf(os, suffix);
329 }
330}
331
332void
330 const SymbolTable *symtab,
331 const std::string &prefix,
332 const Addr addr,
333 const std::string &suffix) const
334{
335 Addr symbolAddr;
336 std::string symbol;
337 if (symtab && symtab->findNearestSymbol(addr, symbol, symbolAddr)) {
338 ccprintf(os, "%s%s", prefix, symbol);
339 if (symbolAddr != addr)
340 ccprintf(os, "+%d", addr - symbolAddr);
341 ccprintf(os, suffix);
342 }
343}
344
345void
333ArmStaticInst::printShiftOperand(std::ostream &os) const
346ArmStaticInstBase::printShiftOperand(std::ostream &os) const
334{
335 printReg(os, machInst.rm);
336
337 bool immShift = (machInst.opcode4 == 0);
338 bool done = false;
339 unsigned shiftAmt = (machInst.shiftSize);
340 ArmShiftType type = (ArmShiftType)(uint32_t)machInst.shift;
341

--- 30 unchanged lines hidden (view full) ---

372 if (immShift)
373 os << "#" << shiftAmt;
374 else
375 printReg(os, machInst.rs);
376 }
377}
378
379void
347{
348 printReg(os, machInst.rm);
349
350 bool immShift = (machInst.opcode4 == 0);
351 bool done = false;
352 unsigned shiftAmt = (machInst.shiftSize);
353 ArmShiftType type = (ArmShiftType)(uint32_t)machInst.shift;
354

--- 30 unchanged lines hidden (view full) ---

385 if (immShift)
386 os << "#" << shiftAmt;
387 else
388 printReg(os, machInst.rs);
389 }
390}
391
392void
380ArmStaticInst::printDataInst(std::ostream &os, bool withImm) const
393ArmStaticInstBase::printDataInst(std::ostream &os, bool withImm) const
381{
382 printMnemonic(os, machInst.sField ? "s" : "");
383 //XXX It would be nice if the decoder figured this all out for us.
384 unsigned opcode = machInst.opcode;
385 bool firstOp = true;
386
387 // Destination
388 // Cmp, cmn, teq, and tst don't have one.

--- 18 unchanged lines hidden (view full) ---

407 uint32_t imm = machInst.imm;
408 ccprintf(os, "#%#x", (imm << (32 - rotate)) | (imm >> rotate));
409 } else {
410 printShiftOperand(os);
411 }
412}
413
414std::string
394{
395 printMnemonic(os, machInst.sField ? "s" : "");
396 //XXX It would be nice if the decoder figured this all out for us.
397 unsigned opcode = machInst.opcode;
398 bool firstOp = true;
399
400 // Destination
401 // Cmp, cmn, teq, and tst don't have one.

--- 18 unchanged lines hidden (view full) ---

420 uint32_t imm = machInst.imm;
421 ccprintf(os, "#%#x", (imm << (32 - rotate)) | (imm >> rotate));
422 } else {
423 printShiftOperand(os);
424 }
425}
426
427std::string
415ArmStaticInst::generateDisassembly(Addr pc,
428ArmStaticInstBase::generateDisassembly(Addr pc,
416 const SymbolTable *symtab) const
417{
418 std::stringstream ss;
419 printMnemonic(ss);
420 return ss.str();
421}
422}
429 const SymbolTable *symtab) const
430{
431 std::stringstream ss;
432 printMnemonic(ss);
433 return ss.str();
434}
435}