static_inst.cc (12403:7be05f61abf3) static_inst.cc (12497:cbc435d1d7c0)
1/*
1/*
2 * Copyright (c) 2010-2014, 2016-2017 ARM Limited
2 * Copyright (c) 2010-2014, 2016-2018 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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892illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr)
893{
894 const OperatingMode mode = (OperatingMode) (uint8_t)spsr.mode;
895 if (badMode(mode))
896 return true;
897
898 const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
899 const ExceptionLevel target_el = opModeToEL(mode);
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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892illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR spsr)
893{
894 const OperatingMode mode = (OperatingMode) (uint8_t)spsr.mode;
895 if (badMode(mode))
896 return true;
897
898 const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
899 const ExceptionLevel target_el = opModeToEL(mode);
900
901 HCR hcr = ((HCR)tc->readMiscReg(MISCREG_HCR_EL2));
902 SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3));
903
900 if (target_el > opModeToEL(cur_mode))
901 return true;
902
904 if (target_el > opModeToEL(cur_mode))
905 return true;
906
903 if (target_el == EL3 && !ArmSystem::haveSecurity(tc))
907 if (!ArmSystem::haveEL(tc, target_el))
904 return true;
905
908 return true;
909
906 if (target_el == EL2 && !ArmSystem::haveVirtualization(tc))
910 if (target_el == EL1 && ArmSystem::haveEL(tc, EL2) && scr.ns && hcr.tge)
907 return true;
908
911 return true;
912
913 if (target_el == EL2 && ArmSystem::haveEL(tc, EL3) && !scr.ns)
914 return true;
915
916 bool spsr_mode_is_aarch32 = (spsr.width == 1);
917 bool known, target_el_is_aarch32;
918 std::tie(known, target_el_is_aarch32) = ELUsingAArch32K(tc, target_el);
919 assert(known || (target_el == EL0 && ELIs64(tc, EL1)));
920
921 if (known && (spsr_mode_is_aarch32 != target_el_is_aarch32))
922 return true;
923
909 if (!spsr.width) {
910 // aarch64
911 if (!ArmSystem::highestELIs64(tc))
912 return true;
924 if (!spsr.width) {
925 // aarch64
926 if (!ArmSystem::highestELIs64(tc))
927 return true;
913
914 if (spsr & 0x2)
915 return true;
916 if (target_el == EL0 && spsr.sp)
917 return true;
928 if (spsr & 0x2)
929 return true;
930 if (target_el == EL0 && spsr.sp)
931 return true;
918 if (target_el == EL2 && !((SCR)tc->readMiscReg(MISCREG_SCR_EL3)).ns)
919 return false;
920 } else {
932 } else {
933 // aarch32
921 return badMode32(mode);
922 }
923
924 return false;
925}
926
927CPSR
928ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const

--- 45 unchanged lines hidden --- 		934 return badMode32(mode);
935 }
936
937 return false;
938}
939
940CPSR
941ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const

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