static_inst.cc (11793:ef606668d247) static_inst.cc (12104:edd63f9c6184)
1/*
2 * Copyright (c) 2010-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 277 unchanged lines hidden (view full) ---

286 default:
287 ccprintf(std::cerr, "Unhandled shift type\n");
288 exit(1);
289 break;
290 }
291 return 0;
292}
293
1/*
2 * Copyright (c) 2010-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 277 unchanged lines hidden (view full) ---

286 default:
287 ccprintf(std::cerr, "Unhandled shift type\n");
288 exit(1);
289 break;
290 }
291 return 0;
292}
293
294
295void
294void
296ArmStaticInst::printReg(std::ostream &os, int reg) const
295ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx) const
297{
296{
298 RegIndex rel_reg;
299
300 switch (regIdxToClass(reg, &rel_reg)) {
301 case IntRegClass:
302 if (aarch64) {
303 if (reg == INTREG_UREG0)
304 ccprintf(os, "ureg0");
305 else if (reg == INTREG_SPX)
306 ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
307 else if (reg == INTREG_X31)
308 ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
309 else
310 ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg);
311 } else {
312 switch (rel_reg) {
313 case PCReg:
314 ccprintf(os, "pc");
315 break;
316 case StackPointerReg:
317 ccprintf(os, "sp");
318 break;
319 case FramePointerReg:
320 ccprintf(os, "fp");
321 break;
322 case ReturnAddressReg:
323 ccprintf(os, "lr");
324 break;
325 default:
326 ccprintf(os, "r%d", reg);
327 break;
328 }
297 if (aarch64) {
298 if (reg_idx == INTREG_UREG0)
299 ccprintf(os, "ureg0");
300 else if (reg_idx == INTREG_SPX)
301 ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
302 else if (reg_idx == INTREG_X31)
303 ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
304 else
305 ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg_idx);
306 } else {
307 switch (reg_idx) {
308 case PCReg:
309 ccprintf(os, "pc");
310 break;
311 case StackPointerReg:
312 ccprintf(os, "sp");
313 break;
314 case FramePointerReg:
315 ccprintf(os, "fp");
316 break;
317 case ReturnAddressReg:
318 ccprintf(os, "lr");
319 break;
320 default:
321 ccprintf(os, "r%d", reg_idx);
322 break;
329 }
323 }
330 break;
331 case FloatRegClass:
332 ccprintf(os, "f%d", rel_reg);
333 break;
334 case MiscRegClass:
335 assert(rel_reg < NUM_MISCREGS);
336 ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
337 break;
338 case CCRegClass:
339 ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
340 break;
341 }
342}
343
344void
324 }
325}
326
327void
328ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
329{
330 ccprintf(os, "f%d", reg_idx);
331}
332
333void
334ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
335{
336 ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]);
337}
338
339void
340ArmStaticInst::printMiscReg(std::ostream &os, RegIndex reg_idx) const
341{
342 assert(reg_idx < NUM_MISCREGS);
343 ccprintf(os, "%s", ArmISA::miscRegName[reg_idx]);
344}
345
346void
345ArmStaticInst::printMnemonic(std::ostream &os,
346 const std::string &suffix,
347 bool withPred,
348 bool withCond64,
349 ConditionCode cond64) const
350{
351 os << " " << mnemonic;
352 if (withPred && !aarch64) {

--- 113 unchanged lines hidden (view full) ---

466 bool immShift,
467 uint32_t shiftAmt,
468 IntRegIndex rs,
469 ArmShiftType type) const
470{
471 bool firstOp = false;
472
473 if (rm != INTREG_ZERO) {
347ArmStaticInst::printMnemonic(std::ostream &os,
348 const std::string &suffix,
349 bool withPred,
350 bool withCond64,
351 ConditionCode cond64) const
352{
353 os << " " << mnemonic;
354 if (withPred && !aarch64) {

--- 113 unchanged lines hidden (view full) ---

468 bool immShift,
469 uint32_t shiftAmt,
470 IntRegIndex rs,
471 ArmShiftType type) const
472{
473 bool firstOp = false;
474
475 if (rm != INTREG_ZERO) {
474 printReg(os, rm);
476 printIntReg(os, rm);
475 }
476
477 bool done = false;
478
479 if ((type == LSR || type == ASR) && immShift && shiftAmt == 0)
480 shiftAmt = 32;
481
482 switch (type) {

--- 32 unchanged lines hidden (view full) ---

515 panic("Tried to disassemble unrecognized shift type.\n");
516 }
517 if (!done) {
518 if (!firstOp)
519 os << " ";
520 if (immShift)
521 os << "#" << shiftAmt;
522 else
477 }
478
479 bool done = false;
480
481 if ((type == LSR || type == ASR) && immShift && shiftAmt == 0)
482 shiftAmt = 32;
483
484 switch (type) {

--- 32 unchanged lines hidden (view full) ---

517 panic("Tried to disassemble unrecognized shift type.\n");
518 }
519 if (!done) {
520 if (!firstOp)
521 os << " ";
522 if (immShift)
523 os << "#" << shiftAmt;
524 else
523 printReg(os, rs);
525 printIntReg(os, rs);
524 }
525}
526
527void
528ArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os,
529 IntRegIndex rm, ArmExtendType type,
530 int64_t shiftAmt) const
531{
532 if (!firstOperand)
533 ccprintf(os, ", ");
526 }
527}
528
529void
530ArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os,
531 IntRegIndex rm, ArmExtendType type,
532 int64_t shiftAmt) const
533{
534 if (!firstOperand)
535 ccprintf(os, ", ");
534 printReg(os, rm);
536 printIntReg(os, rm);
535 if (type == UXTX && shiftAmt == 0)
536 return;
537 switch (type) {
538 case UXTB: ccprintf(os, ", UXTB");
539 break;
540 case UXTH: ccprintf(os, ", UXTH");
541 break;
542 case UXTW: ccprintf(os, ", UXTW");

--- 20 unchanged lines hidden (view full) ---

563 ArmShiftType type, uint64_t imm) const
564{
565 printMnemonic(os, s ? "s" : "");
566 bool firstOp = true;
567
568 // Destination
569 if (rd != INTREG_ZERO) {
570 firstOp = false;
537 if (type == UXTX && shiftAmt == 0)
538 return;
539 switch (type) {
540 case UXTB: ccprintf(os, ", UXTB");
541 break;
542 case UXTH: ccprintf(os, ", UXTH");
543 break;
544 case UXTW: ccprintf(os, ", UXTW");

--- 20 unchanged lines hidden (view full) ---

565 ArmShiftType type, uint64_t imm) const
566{
567 printMnemonic(os, s ? "s" : "");
568 bool firstOp = true;
569
570 // Destination
571 if (rd != INTREG_ZERO) {
572 firstOp = false;
571 printReg(os, rd);
573 printIntReg(os, rd);
572 }
573
574 // Source 1.
575 if (rn != INTREG_ZERO) {
576 if (!firstOp)
577 os << ", ";
578 firstOp = false;
574 }
575
576 // Source 1.
577 if (rn != INTREG_ZERO) {
578 if (!firstOp)
579 os << ", ";
580 firstOp = false;
579 printReg(os, rn);
581 printIntReg(os, rn);
580 }
581
582 if (!firstOp)
583 os << ", ";
584 if (withImm) {
585 ccprintf(os, "#%ld", imm);
586 } else {
587 printShiftOperand(os, rm, immShift, shiftAmt, rs, type);

--- 255 unchanged lines hidden --- 		582 }
583
584 if (!firstOp)
585 os << ", ";
586 if (withImm) {
587 ccprintf(os, "#%ld", imm);
588 } else {
589 printShiftOperand(os, rm, immShift, shiftAmt, rs, type);

--- 255 unchanged lines hidden ---