static_inst.cc (10934:5af8f40d8f2c) static_inst.cc (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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332 break;
333 case MiscRegClass:
334 assert(rel_reg < NUM_MISCREGS);
335 ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
336 break;
337 case CCRegClass:
338 ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
339 break;
1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 323 unchanged lines hidden (view full) ---

332 break;
333 case MiscRegClass:
334 assert(rel_reg < NUM_MISCREGS);
335 ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
336 break;
337 case CCRegClass:
338 ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
339 break;
340 case VectorRegClass:
341 panic("ARM ISA does not have any vector registers yet!");
342 }
343}
344
345void
346ArmStaticInst::printMnemonic(std::ostream &os,
347 const std::string &suffix,
348 bool withPred,
349 bool withCond64,

--- 251 unchanged lines hidden --- 		340 }
341}
342
343void
344ArmStaticInst::printMnemonic(std::ostream &os,
345 const std::string &suffix,
346 bool withPred,
347 bool withCond64,

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