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<
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< ArmStaticInst::printReg(std::ostream &os, int reg) const
---
> ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx) const
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< RegIndex rel_reg;
<
< switch (regIdxToClass(reg, &rel_reg)) {
< case IntRegClass:
< if (aarch64) {
< if (reg == INTREG_UREG0)
< ccprintf(os, "ureg0");
< else if (reg == INTREG_SPX)
< ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
< else if (reg == INTREG_X31)
< ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
< else
< ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg);
< } else {
< switch (rel_reg) {
< case PCReg:
< ccprintf(os, "pc");
< break;
< case StackPointerReg:
< ccprintf(os, "sp");
< break;
< case FramePointerReg:
< ccprintf(os, "fp");
< break;
< case ReturnAddressReg:
< ccprintf(os, "lr");
< break;
< default:
< ccprintf(os, "r%d", reg);
< break;
< }
---
> if (aarch64) {
> if (reg_idx == INTREG_UREG0)
> ccprintf(os, "ureg0");
> else if (reg_idx == INTREG_SPX)
> ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
> else if (reg_idx == INTREG_X31)
> ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
> else
> ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg_idx);
> } else {
> switch (reg_idx) {
> case PCReg:
> ccprintf(os, "pc");
> break;
> case StackPointerReg:
> ccprintf(os, "sp");
> break;
> case FramePointerReg:
> ccprintf(os, "fp");
> break;
> case ReturnAddressReg:
> ccprintf(os, "lr");
> break;
> default:
> ccprintf(os, "r%d", reg_idx);
> break;
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< break;
< case FloatRegClass:
< ccprintf(os, "f%d", rel_reg);
< break;
< case MiscRegClass:
< assert(rel_reg < NUM_MISCREGS);
< ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
< break;
< case CCRegClass:
< ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]);
< break;
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> ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
> {
> ccprintf(os, "f%d", reg_idx);
> }
>
> void
> ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
> {
> ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]);
> }
>
> void
> ArmStaticInst::printMiscReg(std::ostream &os, RegIndex reg_idx) const
> {
> assert(reg_idx < NUM_MISCREGS);
> ccprintf(os, "%s", ArmISA::miscRegName[reg_idx]);
> }
>
> void
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< printReg(os, rm);
---
> printIntReg(os, rm);
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< printReg(os, rs);
---
> printIntReg(os, rs);
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< printReg(os, rm);
---
> printIntReg(os, rm);
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< printReg(os, rd);
---
> printIntReg(os, rd);
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< printReg(os, rn);
---
> printIntReg(os, rn);