1/*
2 * Copyright (c) 2010 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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81 default:
82 ccprintf(std::cerr, "Unhandled shift type\n");
83 exit(1);
84 break;
85 }
86 return 0;
87}
88
89// Shift Rm by Rs
90int32_t
91ArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt,
92 uint32_t type, uint32_t cfval) const
93{
94 enum ArmShiftType shiftType;
95 shiftType = (enum ArmShiftType) type;
96

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209
210void
211ArmStaticInst::printReg(std::ostream &os, int reg) const
212{
213 RegIndex rel_reg;
214
215 switch (regIdxToClass(reg, &rel_reg)) {
216 case IntRegClass:
217 switch (rel_reg) {
218 case PCReg:
219 ccprintf(os, "pc");
220 break;
221 case StackPointerReg:
222 ccprintf(os, "sp");
223 break;
224 case FramePointerReg:
225 ccprintf(os, "fp");
226 break;
227 case ReturnAddressReg:
228 ccprintf(os, "lr");
229 break;
230 default:
231 ccprintf(os, "r%d", reg);
232 break;
233 }
234 break;
235 case FloatRegClass:
236 ccprintf(os, "f%d", rel_reg);
237 break;
238 case MiscRegClass:
239 assert(rel_reg < NUM_MISCREGS);
240 ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]);
241 break;
242 case CCRegClass:
243 panic("printReg: CCRegClass but ARM has no CC regs\n");
244 }
245}
246
247void
248ArmStaticInst::printMnemonic(std::ostream &os,
249 const std::string &suffix,
250 bool withPred) const
251{
252 os << " " << mnemonic;
253 if (withPred) {
254 unsigned condCode = machInst.condCode;
255 switch (condCode) {
256 case COND_EQ:
257 os << "eq";
258 break;
259 case COND_NE:
260 os << "ne";
261 break;
262 case COND_CS:
263 os << "cs";
264 break;
265 case COND_CC:
266 os << "cc";
267 break;
268 case COND_MI:
269 os << "mi";
270 break;
271 case COND_PL:
272 os << "pl";
273 break;
274 case COND_VS:
275 os << "vs";
276 break;
277 case COND_VC:
278 os << "vc";
279 break;
280 case COND_HI:
281 os << "hi";
282 break;
283 case COND_LS:
284 os << "ls";
285 break;
286 case COND_GE:
287 os << "ge";
288 break;
289 case COND_LT:
290 os << "lt";
291 break;
292 case COND_GT:
293 os << "gt";
294 break;
295 case COND_LE:
296 os << "le";
297 break;
298 case COND_AL:
299 // This one is implicit.
300 break;
301 case COND_UC:
302 // Unconditional.
303 break;
304 default:
305 panic("Unrecognized condition code %d.\n", condCode);
306 }
307 os << suffix;
308 if (machInst.bigThumb)
309 os << ".w";
310 os << " ";
311 }
312}
313
314void
315ArmStaticInst::printMemSymbol(std::ostream &os,
316 const SymbolTable *symtab,
317 const std::string &prefix,
318 const Addr addr,
319 const std::string &suffix) const
320{
321 Addr symbolAddr;
322 std::string symbol;

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388 if (immShift)
389 os << "#" << shiftAmt;
390 else
391 printReg(os, rs);
392 }
393}
394
395void
396ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
397 bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
398 IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
399 ArmShiftType type, uint32_t imm) const
400{
401 printMnemonic(os, s ? "s" : "");
402 bool firstOp = true;
403

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