1/*
2 * Copyright (c) 2010-2014, 2016 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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286 default:
287 ccprintf(std::cerr, "Unhandled shift type\n");
288 exit(1);
289 break;
290 }
291 return 0;
292}
293
294void
295ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx) const
296{
297 if (aarch64) {
298 if (reg_idx == INTREG_UREG0)
299 ccprintf(os, "ureg0");
300 else if (reg_idx == INTREG_SPX)
301 ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp");
302 else if (reg_idx == INTREG_X31)
303 ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x");
304 else
305 ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg_idx);
306 } else {
307 switch (reg_idx) {
308 case PCReg:
309 ccprintf(os, "pc");
310 break;
311 case StackPointerReg:
312 ccprintf(os, "sp");
313 break;
314 case FramePointerReg:
315 ccprintf(os, "fp");
316 break;
317 case ReturnAddressReg:
318 ccprintf(os, "lr");
319 break;
320 default:
321 ccprintf(os, "r%d", reg_idx);
322 break;
323 }
324 }
325}
326
327void
328ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
329{
330 ccprintf(os, "f%d", reg_idx);
331}
332
333void
334ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
335{
336 ccprintf(os, "cc_%s", ArmISA::ccRegName[reg_idx]);
337}
338
339void
340ArmStaticInst::printMiscReg(std::ostream &os, RegIndex reg_idx) const
341{
342 assert(reg_idx < NUM_MISCREGS);
343 ccprintf(os, "%s", ArmISA::miscRegName[reg_idx]);
344}
345
346void
347ArmStaticInst::printMnemonic(std::ostream &os,
348 const std::string &suffix,
349 bool withPred,
350 bool withCond64,
351 ConditionCode cond64) const
352{
353 os << " " << mnemonic;
354 if (withPred && !aarch64) {

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468 bool immShift,
469 uint32_t shiftAmt,
470 IntRegIndex rs,
471 ArmShiftType type) const
472{
473 bool firstOp = false;
474
475 if (rm != INTREG_ZERO) {
476 printIntReg(os, rm);
477 }
478
479 bool done = false;
480
481 if ((type == LSR || type == ASR) && immShift && shiftAmt == 0)
482 shiftAmt = 32;
483
484 switch (type) {

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517 panic("Tried to disassemble unrecognized shift type.\n");
518 }
519 if (!done) {
520 if (!firstOp)
521 os << " ";
522 if (immShift)
523 os << "#" << shiftAmt;
524 else
525 printIntReg(os, rs);
526 }
527}
528
529void
530ArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os,
531 IntRegIndex rm, ArmExtendType type,
532 int64_t shiftAmt) const
533{
534 if (!firstOperand)
535 ccprintf(os, ", ");
536 printIntReg(os, rm);
537 if (type == UXTX && shiftAmt == 0)
538 return;
539 switch (type) {
540 case UXTB: ccprintf(os, ", UXTB");
541 break;
542 case UXTH: ccprintf(os, ", UXTH");
543 break;
544 case UXTW: ccprintf(os, ", UXTW");

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565 ArmShiftType type, uint64_t imm) const
566{
567 printMnemonic(os, s ? "s" : "");
568 bool firstOp = true;
569
570 // Destination
571 if (rd != INTREG_ZERO) {
572 firstOp = false;
573 printIntReg(os, rd);
574 }
575
576 // Source 1.
577 if (rn != INTREG_ZERO) {
578 if (!firstOp)
579 os << ", ";
580 firstOp = false;
581 printIntReg(os, rn);
582 }
583
584 if (!firstOp)
585 os << ", ";
586 if (withImm) {
587 ccprintf(os, "#%ld", imm);
588 } else {
589 printShiftOperand(os, rm, immShift, shiftAmt, rs, type);

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