pseudo.hh (11572:9eac6e12c673) pseudo.hh (12530:ab63172c4fbe)
1/*
1/*
2 * Copyright (c) 2014,2016 ARM Limited
2 * Copyright (c) 2014,2016,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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118/**
119 * Certain mrc/mcr instructions act as nops or flush the pipe based on what
120 * register the instruction is trying to access. This inst/class exists so that
121 * we can still check for hyp traps, as the normal nop instruction
122 * does not.
123 */
124class McrMrcMiscInst : public ArmStaticInst
125{
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 107 unchanged lines hidden (view full) ---

118/**
119 * Certain mrc/mcr instructions act as nops or flush the pipe based on what
120 * register the instruction is trying to access. This inst/class exists so that
121 * we can still check for hyp traps, as the normal nop instruction
122 * does not.
123 */
124class McrMrcMiscInst : public ArmStaticInst
125{
126 private:
126 protected:
127 uint64_t iss;
128 MiscRegIndex miscReg;
129
130 public:
131 McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
132 uint64_t _iss, MiscRegIndex _miscReg);
133
134 Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
135
136 std::string
137 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
138
139};
140
127 uint64_t iss;
128 MiscRegIndex miscReg;
129
130 public:
131 McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
132 uint64_t _iss, MiscRegIndex _miscReg);
133
134 Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
135
136 std::string
137 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
138
139};
140
141/**
142 * This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc
143 * behaviour is trappable even for unimplemented registers.
144 */
145class McrMrcImplDefined : public McrMrcMiscInst
146{
147 public:
148 McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst,
149 uint64_t _iss, MiscRegIndex _miscReg);
150
151 Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
152
153 std::string
154 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
155
156};
157
141#endif
158#endif