1/* 2 * Copyright (c) 2014,2016,2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 42 unchanged lines hidden (view full) --- 51 protected: 52 DecoderFault faultId; 53 54 const char *faultName() const; 55 56 public: 57 DecoderFaultInst(ExtMachInst _machInst); 58 |
59 Fault execute(ExecContext *xc, 60 Trace::InstRecord *traceData) const override; |
61 |
62 std::string generateDisassembly( 63 Addr pc, const SymbolTable *symtab) const override; |
64}; 65 66/** 67 * Static instruction class for unimplemented instructions that 68 * cause simulator termination. Note that these are recognized 69 * (legal) instructions that the simulator does not support; the 70 * 'Unknown' class is used for unrecognized/illegal instructions. 71 * This is a leaf class. --- 5 unchanged lines hidden (view full) --- 77 /// coproc. register name 78 std::string fullMnemonic; 79 80 public: 81 FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst); 82 FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst, 83 const std::string& _fullMnemonic); 84 |
85 Fault execute(ExecContext *xc, 86 Trace::InstRecord *traceData) const override; |
87 |
88 std::string generateDisassembly( 89 Addr pc, const SymbolTable *symtab) const override; |
90}; 91 92/** 93 * Base class for unimplemented instructions that cause a warning 94 * to be printed (but do not terminate simulation). This 95 * implementation is a little screwy in that it will print a 96 * warning for each instance of a particular unimplemented machine 97 * instruction, not just for each unimplemented opcode. Should --- 9 unchanged lines hidden (view full) --- 107 /// coproc. register name 108 std::string fullMnemonic; 109 110 public: 111 WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst); 112 WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst, 113 const std::string& _fullMnemonic); 114 |
115 Fault execute(ExecContext *xc, 116 Trace::InstRecord *traceData) const override; |
117 |
118 std::string generateDisassembly( 119 Addr pc, const SymbolTable *symtab) const override; |
120}; 121 122/** 123 * Certain mrc/mcr instructions act as nops or flush the pipe based on what 124 * register the instruction is trying to access. This inst/class exists so that 125 * we can still check for hyp traps, as the normal nop instruction 126 * does not. 127 */ 128class McrMrcMiscInst : public ArmStaticInst 129{ 130 protected: 131 uint64_t iss; 132 MiscRegIndex miscReg; 133 134 public: 135 McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, 136 uint64_t _iss, MiscRegIndex _miscReg); 137 |
138 Fault execute(ExecContext *xc, 139 Trace::InstRecord *traceData) const override; |
140 |
141 std::string generateDisassembly( 142 Addr pc, const SymbolTable *symtab) const override; |
143 144}; 145 146/** 147 * This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc 148 * behaviour is trappable even for unimplemented registers. 149 */ 150class McrMrcImplDefined : public McrMrcMiscInst 151{ 152 public: 153 McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst, 154 uint64_t _iss, MiscRegIndex _miscReg); 155 |
156 Fault execute(ExecContext *xc, 157 Trace::InstRecord *traceData) const override; |
158 |
159 std::string generateDisassembly( 160 Addr pc, const SymbolTable *symtab) const override; |
161 162}; 163 164#endif |