1/*
2 * Copyright (c) 2014,2016,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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51 protected:
52 DecoderFault faultId;
53
54 const char *faultName() const;
55
56 public:
57 DecoderFaultInst(ExtMachInst _machInst);
58
59 Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
60
61 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
62};
63
64/**
65 * Static instruction class for unimplemented instructions that
66 * cause simulator termination. Note that these are recognized
67 * (legal) instructions that the simulator does not support; the
68 * 'Unknown' class is used for unrecognized/illegal instructions.
69 * This is a leaf class.

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75 /// coproc. register name
76 std::string fullMnemonic;
77
78 public:
79 FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
80 FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
81 const std::string& _fullMnemonic);
82
83 Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
84
85 std::string
86 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
87};
88
89/**
90 * Base class for unimplemented instructions that cause a warning
91 * to be printed (but do not terminate simulation). This
92 * implementation is a little screwy in that it will print a
93 * warning for each instance of a particular unimplemented machine
94 * instruction, not just for each unimplemented opcode. Should

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104 /// coproc. register name
105 std::string fullMnemonic;
106
107 public:
108 WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
109 WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
110 const std::string& _fullMnemonic);
111
112 Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
113
114 std::string
115 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
116};
117
118/**
119 * Certain mrc/mcr instructions act as nops or flush the pipe based on what
120 * register the instruction is trying to access. This inst/class exists so that
121 * we can still check for hyp traps, as the normal nop instruction
122 * does not.
123 */
124class McrMrcMiscInst : public ArmStaticInst
125{
126 protected:
127 uint64_t iss;
128 MiscRegIndex miscReg;
129
130 public:
131 McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
132 uint64_t _iss, MiscRegIndex _miscReg);
133
134 Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
135
136 std::string
137 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
138
139};
140
141/**
142 * This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc
143 * behaviour is trappable even for unimplemented registers.
144 */
145class McrMrcImplDefined : public McrMrcMiscInst
146{
147 public:
148 McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst,
149 uint64_t _iss, MiscRegIndex _miscReg);
150
151 Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const;
152
153 std::string
154 generateDisassembly(Addr pc, const SymbolTable *symtab) const;
155
156};
157
158#endif