1/*
2 * Copyright (c) 2014,2016,2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andreas Sandberg
41 * Stephen Hines
42 */
43
44#ifndef __ARCH_ARM_INSTS_PSEUDO_HH__
45#define __ARCH_ARM_INSTS_PSEUDO_HH__
46
47#include "arch/arm/insts/static_inst.hh"
48
49class DecoderFaultInst : public ArmStaticInst
50{
51 protected:
52 DecoderFault faultId;
53
54 const char *faultName() const;
55
56 public:
57 DecoderFaultInst(ExtMachInst _machInst);
58
59 Fault execute(ExecContext *xc,
60 Trace::InstRecord *traceData) const override;
61
62 std::string generateDisassembly(
63 Addr pc, const SymbolTable *symtab) const override;
64};
65
66/**
67 * Static instruction class for unimplemented instructions that
68 * cause simulator termination. Note that these are recognized
69 * (legal) instructions that the simulator does not support; the
70 * 'Unknown' class is used for unrecognized/illegal instructions.
71 * This is a leaf class.
72 */
73class FailUnimplemented : public ArmStaticInst
74{
75 private:
76 /// Full mnemonic for MRC and MCR instructions including the
77 /// coproc. register name
78 std::string fullMnemonic;
79
80 public:
81 FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
82 FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
83 const std::string& _fullMnemonic);
84
85 Fault execute(ExecContext *xc,
86 Trace::InstRecord *traceData) const override;
87
88 std::string generateDisassembly(
89 Addr pc, const SymbolTable *symtab) const override;
90};
91
92/**
93 * Base class for unimplemented instructions that cause a warning
94 * to be printed (but do not terminate simulation). This
95 * implementation is a little screwy in that it will print a
96 * warning for each instance of a particular unimplemented machine
97 * instruction, not just for each unimplemented opcode. Should
98 * probably make the 'warned' flag a static member of the derived
99 * class.
100 */
101class WarnUnimplemented : public ArmStaticInst
102{
103 private:
104 /// Have we warned on this instruction yet?
105 mutable bool warned;
106 /// Full mnemonic for MRC and MCR instructions including the
107 /// coproc. register name
108 std::string fullMnemonic;
109
110 public:
111 WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst);
112 WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
113 const std::string& _fullMnemonic);
114
115 Fault execute(ExecContext *xc,
116 Trace::InstRecord *traceData) const override;
117
118 std::string generateDisassembly(
119 Addr pc, const SymbolTable *symtab) const override;
120};
121
122/**
123 * Certain mrc/mcr instructions act as nops or flush the pipe based on what
124 * register the instruction is trying to access. This inst/class exists so that
125 * we can still check for hyp traps, as the normal nop instruction
126 * does not.
127 */
128class McrMrcMiscInst : public ArmStaticInst
129{
130 protected:
131 uint64_t iss;
132 MiscRegIndex miscReg;
133
134 public:
135 McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
136 uint64_t _iss, MiscRegIndex _miscReg);
137
138 Fault execute(ExecContext *xc,
139 Trace::InstRecord *traceData) const override;
140
141 std::string generateDisassembly(
142 Addr pc, const SymbolTable *symtab) const override;
143
144};
145
146/**
147 * This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc
148 * behaviour is trappable even for unimplemented registers.
149 */
150class McrMrcImplDefined : public McrMrcMiscInst
151{
152 public:
153 McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst,
154 uint64_t _iss, MiscRegIndex _miscReg);
155
156 Fault execute(ExecContext *xc,
157 Trace::InstRecord *traceData) const override;
158
159 std::string generateDisassembly(
160 Addr pc, const SymbolTable *symtab) const override;
161
162};
163
164#endif