pseudo.cc (12260:91f39e81ac12) | pseudo.cc (12530:ab63172c4fbe) |
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1/* | 1/* |
2 * Copyright (c) 2014,2016-2017 ARM Limited | 2 * Copyright (c) 2014,2016-2018 ARM Limited |
3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 165 unchanged lines hidden (view full) --- 176 177std::string 178WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const 179{ 180 return csprintf("%-10s (unimplemented)", 181 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic); 182} 183 | 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 165 unchanged lines hidden (view full) --- 176 177std::string 178WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const 179{ 180 return csprintf("%-10s (unimplemented)", 181 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic); 182} 183 |
184 185 | |
186McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, | 184McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, |
187 uint64_t _iss, MiscRegIndex _miscReg) | 185 uint64_t _iss, MiscRegIndex _miscReg) |
188 : ArmStaticInst(_mnemonic, _machInst, No_OpClass) 189{ 190 flags[IsNonSpeculative] = true; 191 iss = _iss; 192 miscReg = _miscReg; 193} 194 195Fault --- 16 unchanged lines hidden (view full) --- 212 } 213} 214 215std::string 216McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const 217{ 218 return csprintf("%-10s (pipe flush)", mnemonic); 219} | 186 : ArmStaticInst(_mnemonic, _machInst, No_OpClass) 187{ 188 flags[IsNonSpeculative] = true; 189 iss = _iss; 190 miscReg = _miscReg; 191} 192 193Fault --- 16 unchanged lines hidden (view full) --- 210 } 211} 212 213std::string 214McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const 215{ 216 return csprintf("%-10s (pipe flush)", mnemonic); 217} |
218 219McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic, 220 ExtMachInst _machInst, uint64_t _iss, 221 MiscRegIndex _miscReg) 222 : McrMrcMiscInst(_mnemonic, _machInst, _iss, _miscReg) 223{} 224 225Fault 226McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const 227{ 228 uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR); 229 uint32_t hcr = xc->readMiscReg(MISCREG_HCR); 230 uint32_t scr = xc->readMiscReg(MISCREG_SCR); 231 uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR); 232 uint32_t hstr = xc->readMiscReg(MISCREG_HSTR); 233 uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR); 234 235 bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr, 236 hcptr, iss); 237 if (hypTrap) { 238 return std::make_shared<HypervisorTrap>(machInst, iss, 239 EC_TRAPPED_CP15_MCR_MRC); 240 } else { 241 return std::make_shared<UndefinedInstruction>(machInst, false, 242 mnemonic); 243 } 244} 245 246std::string 247McrMrcImplDefined::generateDisassembly(Addr pc, 248 const SymbolTable *symtab) const 249{ 250 return csprintf("%-10s (implementation defined)", mnemonic); 251} |
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