pseudo.cc (10696:b5e5068fcb26) pseudo.cc (11572:9eac6e12c673)
1/*
1/*
2 * Copyright (c) 2014 ARM Limited
2 * Copyright (c) 2014,2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 166 unchanged lines hidden (view full) ---

177WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
178{
179 return csprintf("%-10s (unimplemented)",
180 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
181}
182
183
184
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 166 unchanged lines hidden (view full) ---

177WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const
178{
179 return csprintf("%-10s (unimplemented)",
180 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
181}
182
183
184
185FlushPipeInst::FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst)
185McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
186 uint64_t _iss, MiscRegIndex _miscReg)
186 : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
187{
188 flags[IsNonSpeculative] = true;
187 : ArmStaticInst(_mnemonic, _machInst, No_OpClass)
188{
189 flags[IsNonSpeculative] = true;
190 iss = _iss;
191 miscReg = _miscReg;
189}
190
191Fault
192}
193
194Fault
192FlushPipeInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
195McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
193{
196{
194 Fault fault = std::make_shared<FlushPipe>();
195 return fault;
197 uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
198 uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
199 uint32_t scr = xc->readMiscReg(MISCREG_SCR);
200 uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
201 uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
202 uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
203
204 bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
205 hcptr, iss);
206 if (hypTrap) {
207 return std::make_shared<HypervisorTrap>(machInst, iss,
208 EC_TRAPPED_CP15_MCR_MRC);
209 }
210
211 if (miscReg == MISCREG_DCCMVAC)
212 return std::make_shared<FlushPipe>();
213 else
214 return NoFault;
196}
197
198std::string
215}
216
217std::string
199FlushPipeInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
218McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
200{
201 return csprintf("%-10s (pipe flush)", mnemonic);
202}
219{
220 return csprintf("%-10s (pipe flush)", mnemonic);
221}