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< * Copyright (c) 2014 ARM Limited
---
> * Copyright (c) 2014,2016 ARM Limited
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< FlushPipeInst::FlushPipeInst(const char *_mnemonic, ExtMachInst _machInst)
---
> McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
> uint64_t _iss, MiscRegIndex _miscReg)
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> iss = _iss;
> miscReg = _miscReg;
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< FlushPipeInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
---
> McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
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< Fault fault = std::make_shared<FlushPipe>();
< return fault;
---
> uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR);
> uint32_t hcr = xc->readMiscReg(MISCREG_HCR);
> uint32_t scr = xc->readMiscReg(MISCREG_SCR);
> uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR);
> uint32_t hstr = xc->readMiscReg(MISCREG_HSTR);
> uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR);
>
> bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr,
> hcptr, iss);
> if (hypTrap) {
> return std::make_shared<HypervisorTrap>(machInst, iss,
> EC_TRAPPED_CP15_MCR_MRC);
> }
>
> if (miscReg == MISCREG_DCCMVAC)
> return std::make_shared<FlushPipe>();
> else
> return NoFault;
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< FlushPipeInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
---
> McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const