1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#include "arch/arm/insts/pseudo.hh"
41#include "cpu/exec_context.hh"
42
43DecoderFaultInst::DecoderFaultInst(ExtMachInst _machInst)
44 : ArmStaticInst("gem5decoderFault", _machInst, No_OpClass),
45 faultId(static_cast<DecoderFault>(
46 static_cast<uint8_t>(_machInst.decoderFault)))
47{
48 // Don't call execute() if we're on a speculative path and the
49 // fault is an internal panic fault.
50 flags[IsNonSpeculative] = (faultId == DecoderFault::PANIC);
51}
52
53Fault
54DecoderFaultInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
55{
56 const PCState pc_state(xc->pcState());
57 const Addr pc(pc_state.instAddr());
58
59 switch (faultId) {
60 case DecoderFault::UNALIGNED:
61 if (machInst.aarch64) {
62 return std::make_shared<PCAlignmentFault>(pc);
63 } else {
64 // TODO: We should check if we the receiving end is in
65 // aarch64 mode and raise a PCAlignment fault instead.
66 return std::make_shared<PrefetchAbort>(
67 pc, ArmFault::AlignmentFault);
68 }
69
70 case DecoderFault::PANIC:
71 panic("Internal error in instruction decoder\n");
72
73 case DecoderFault::OK:
74 panic("Decoder fault instruction without decoder fault.\n");
75 }
76
77 panic("Unhandled fault type");
78}
79
80const char *
81DecoderFaultInst::faultName() const
82{
83 switch (faultId) {
84 case DecoderFault::OK:
85 return "OK";
86
87 case DecoderFault::UNALIGNED:
88 return "UnalignedInstruction";
89
90 case DecoderFault::PANIC:
91 return "DecoderPanic";
92 }
93
94 panic("Unhandled fault type");
95}
96
97std::string
98DecoderFaultInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
99{
100 return csprintf("gem5fault %s", faultName());
101}