1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__ 43#define __ARCH_ARM_INSTS_PREDINST_HH__ 44 45#include "arch/arm/insts/static_inst.hh" 46#include "base/trace.hh" 47 48namespace ArmISA 49{ 50static inline uint32_t 51rotate_imm(uint32_t immValue, int rotateValue) 52{ 53 return ((immValue >> (rotateValue & 31)) | 54 (immValue << (32 - (rotateValue & 31)))); 55} 56 57static inline uint32_t 58modified_imm(uint8_t ctrlImm, uint8_t dataImm) 59{ 60 uint32_t bigData = dataImm; 61 uint32_t bigCtrl = ctrlImm; 62 if (bigCtrl < 4) { 63 switch (bigCtrl) { 64 case 0: 65 return bigData; 66 case 1: 67 return bigData | (bigData << 16); 68 case 2: 69 return (bigData << 8) | (bigData << 24); 70 case 3: 71 return (bigData << 0) | (bigData << 8) | 72 (bigData << 16) | (bigData << 24); 73 } 74 } 75 bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1); 76 bigData |= (1 << 7); 77 return bigData << (32 - bigCtrl); 78} 79
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148/** 149 * Base class for predicated integer operations. 150 */ 151class PredOp : public ArmStaticInst 152{ 153 protected: 154 155 ConditionCode condCode; 156 157 /// Constructor 158 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 159 ArmStaticInst(mnem, _machInst, __opClass), 160 condCode((ConditionCode)(unsigned)machInst.condCode) 161 { 162 } 163}; 164 165/** 166 * Base class for predicated immediate operations. 167 */ 168class PredImmOp : public PredOp 169{ 170 protected: 171 172 uint32_t imm; 173 uint32_t rotated_imm; 174 uint32_t rotated_carry; 175 uint32_t rotate; 176 177 /// Constructor 178 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 179 PredOp(mnem, _machInst, __opClass), 180 imm(machInst.imm), rotated_imm(0), rotated_carry(0), 181 rotate(machInst.rotate << 1) 182 { 183 rotated_imm = rotate_imm(imm, rotate); 184 if (rotate != 0) 185 rotated_carry = bits(rotated_imm, 31); 186 } 187 188 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 189}; 190 191/** 192 * Base class for predicated integer operations. 193 */ 194class PredIntOp : public PredOp 195{ 196 protected: 197 198 uint32_t shift_size; 199 uint32_t shift; 200 201 /// Constructor 202 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 203 PredOp(mnem, _machInst, __opClass), 204 shift_size(machInst.shiftSize), shift(machInst.shift) 205 { 206 } 207 208 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 209}; 210 211class DataImmOp : public PredOp 212{ 213 protected: 214 IntRegIndex dest, op1; 215 uint32_t imm; 216 // Whether the carry flag should be modified if that's an option for 217 // this instruction. 218 bool rotC; 219 220 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 221 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) : 222 PredOp(mnem, _machInst, __opClass), 223 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC) 224 {} 225 226 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 227}; 228 229class DataRegOp : public PredOp 230{ 231 protected: 232 IntRegIndex dest, op1, op2; 233 int32_t shiftAmt; 234 ArmShiftType shiftType; 235 236 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 237 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 238 int32_t _shiftAmt, ArmShiftType _shiftType) : 239 PredOp(mnem, _machInst, __opClass), 240 dest(_dest), op1(_op1), op2(_op2), 241 shiftAmt(_shiftAmt), shiftType(_shiftType) 242 {} 243 244 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 245}; 246 247class DataRegRegOp : public PredOp 248{ 249 protected: 250 IntRegIndex dest, op1, op2, shift; 251 ArmShiftType shiftType; 252 253 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 254 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 255 IntRegIndex _shift, ArmShiftType _shiftType) : 256 PredOp(mnem, _machInst, __opClass), 257 dest(_dest), op1(_op1), op2(_op2), shift(_shift), 258 shiftType(_shiftType) 259 {} 260 261 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 262}; 263 264/** 265 * Base class for predicated macro-operations. 266 */ 267class PredMacroOp : public PredOp 268{ 269 protected: 270 271 uint32_t numMicroops; 272 StaticInstPtr * microOps; 273 274 /// Constructor 275 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 276 PredOp(mnem, _machInst, __opClass), 277 numMicroops(0) 278 { 279 // We rely on the subclasses of this object to handle the 280 // initialization of the micro-operations, since they are 281 // all of variable length 282 flags[IsMacroop] = true; 283 } 284 285 ~PredMacroOp() 286 { 287 if (numMicroops) 288 delete [] microOps; 289 } 290 291 StaticInstPtr 292 fetchMicroop(MicroPC microPC) 293 { 294 assert(microPC < numMicroops); 295 return microOps[microPC]; 296 } 297 298 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 299}; 300 301/** 302 * Base class for predicated micro-operations. 303 */ 304class PredMicroop : public PredOp 305{ 306 /// Constructor 307 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 308 PredOp(mnem, _machInst, __opClass) 309 { 310 flags[IsMicroop] = true; 311 } 312}; 313} 314 315#endif //__ARCH_ARM_INSTS_PREDINST_HH__
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