1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43#define __ARCH_ARM_INSTS_PREDINST_HH__
44
45#include "arch/arm/insts/static_inst.hh"
46#include "base/trace.hh"
47
48namespace ArmISA
49{
50static inline uint32_t
51rotate_imm(uint32_t immValue, int rotateValue)
52{
53 return ((immValue >> (rotateValue & 31)) |
54 (immValue << (32 - (rotateValue & 31))));
55}
56
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81/**
82 * Base class for predicated integer operations.
83 */
84class PredOp : public ArmStaticInst
85{
86 protected:
87
88 ConditionCode condCode;
89
90 /// Constructor
91 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
92 ArmStaticInst(mnem, _machInst, __opClass),
93 condCode((ConditionCode)(unsigned)machInst.condCode)
94 {
95 }
96};
97
98/**
99 * Base class for predicated immediate operations.
100 */
101class PredImmOpBase : public PredOp
102{
103 protected:
104
105 uint32_t imm;
106 uint32_t rotated_imm;
107 uint32_t rotated_carry;
108
109 /// Constructor
110 PredImmOpBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
111 PredOp(mnem, _machInst, __opClass),
112 imm(machInst.imm), rotated_imm(0), rotated_carry(0)
113 {
114 }
115
116 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
117};
118
119/**
120 * Base class for regular predicated immediate operations.
121 */
122class PredImmOp : public PredImmOpBase
123{
124 protected:
125
126 uint32_t rotate;
127
128 /// Constructor
129 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
130 PredImmOpBase(mnem, _machInst, __opClass),
131 rotate(machInst.rotate << 1)
132 {
133 rotated_imm = rotate_imm(imm, rotate);
134 if (rotate != 0)
135 rotated_carry = bits(rotated_imm, 31);
136 }
137};
138
139/**
140 * Base class for modified predicated immediate operations.
141 */
142class PredModImmOp : public PredImmOpBase
143{
144 protected:
145
146 uint8_t ctrlImm;
147 uint8_t dataImm;
148
149
150 /// Constructor
151 PredModImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
152 PredImmOpBase(mnem, _machInst, __opClass),
153 ctrlImm(bits(machInst.instBits, 26) << 3 |
154 bits(machInst.instBits, 14, 12)),
155 dataImm(bits(machInst.instBits, 7, 0))
156 {
157 rotated_imm = modified_imm(ctrlImm, dataImm);
158 rotated_carry = bits(rotated_imm, 31);
159 }
160};
161
162/**
163 * Base class for predicated integer operations.
164 */
165class PredIntOp : public PredOp
166{
167 protected:
168
169 uint32_t shift_size;
170 uint32_t shift;
171
172 /// Constructor
173 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
174 PredOp(mnem, _machInst, __opClass),
175 shift_size(machInst.shiftSize), shift(machInst.shift)
176 {
177 }
178
179 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
180};
181
182class DataImmOp : public PredOp
183{
184 protected:
185 IntRegIndex dest, op1;
186 uint32_t imm;
187 // Whether the carry flag should be modified if that's an option for
188 // this instruction.
189 bool rotC;
190
191 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
192 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
193 PredOp(mnem, _machInst, __opClass),
194 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
195 {}
196};
197
198class DataRegOp : public PredOp
199{
200 protected:
201 IntRegIndex dest, op1, op2;
202 int32_t shiftAmt;
203 ArmShiftType shiftType;
204
205 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
206 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
207 int32_t _shiftAmt, ArmShiftType _shiftType) :
208 PredOp(mnem, _machInst, __opClass),
209 dest(_dest), op1(_op1), op2(_op2),
210 shiftAmt(_shiftAmt), shiftType(_shiftType)
211 {}
212};
213
214class DataRegRegOp : public PredOp
215{
216 protected:
217 IntRegIndex dest, op1, op2, shift;
218 ArmShiftType shiftType;
219
220 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
221 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
222 IntRegIndex _shift, ArmShiftType _shiftType) :
223 PredOp(mnem, _machInst, __opClass),
224 dest(_dest), op1(_op1), op2(_op2), shift(_shift),
225 shiftType(_shiftType)
226 {}
227};
228
229/**
230 * Base class for predicated macro-operations.
231 */
232class PredMacroOp : public PredOp
233{
234 protected:
235
236 uint32_t numMicroops;
237 StaticInstPtr * microOps;
238
239 /// Constructor
240 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
241 PredOp(mnem, _machInst, __opClass),
242 numMicroops(0)
243 {
244 // We rely on the subclasses of this object to handle the
245 // initialization of the micro-operations, since they are
246 // all of variable length
247 flags[IsMacroop] = true;
248 }
249
250 ~PredMacroOp()
251 {
252 if (numMicroops)
253 delete [] microOps;
254 }
255
256 StaticInstPtr
257 fetchMicroop(MicroPC microPC)
258 {
259 assert(microPC < numMicroops);
260 return microOps[microPC];
261 }
262
263 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
264};
265
266/**
267 * Base class for predicated micro-operations.
268 */
269class PredMicroop : public PredOp
270{
271 /// Constructor
272 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
273 PredOp(mnem, _machInst, __opClass)
274 {
275 flags[IsMicroop] = true;
276 }
277};
278}
279
280#endif //__ARCH_ARM_INSTS_PREDINST_HH__
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