1/* Copyright (c) 2007-2008 The Florida State University
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
|
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Stephen Hines
28 */
29#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
30#define __ARCH_ARM_INSTS_PREDINST_HH__
31
32#include "arch/arm/insts/static_inst.hh"
33#include "base/trace.hh"
34
35namespace ArmISA
36{
37static inline uint32_t
38rotate_imm(uint32_t immValue, int rotateValue)
39{
40 return ((immValue >> (rotateValue & 31)) |
41 (immValue << (32 - (rotateValue & 31))));
42}
43
44/**
45 * Base class for predicated integer operations.
46 */
47class PredOp : public ArmStaticInst
48{
49 protected:
50
51 ConditionCode condCode;
52
53 /// Constructor
54 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
55 ArmStaticInst(mnem, _machInst, __opClass),
56 condCode((ConditionCode)(unsigned)machInst.condCode)
57 {
58 }
59};
60
61/**
62 * Base class for predicated immediate operations.
63 */
| 15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43#define __ARCH_ARM_INSTS_PREDINST_HH__
44
45#include "arch/arm/insts/static_inst.hh"
46#include "base/trace.hh"
47
48namespace ArmISA
49{
50static inline uint32_t
51rotate_imm(uint32_t immValue, int rotateValue)
52{
53 return ((immValue >> (rotateValue & 31)) |
54 (immValue << (32 - (rotateValue & 31))));
55}
56
57/**
58 * Base class for predicated integer operations.
59 */
60class PredOp : public ArmStaticInst
61{
62 protected:
63
64 ConditionCode condCode;
65
66 /// Constructor
67 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
68 ArmStaticInst(mnem, _machInst, __opClass),
69 condCode((ConditionCode)(unsigned)machInst.condCode)
70 {
71 }
72};
73
74/**
75 * Base class for predicated immediate operations.
76 */
|
64class PredImmOp : public PredOp
| 77class PredImmOpBase : public PredOp
|
65{
66 protected:
67
68 uint32_t imm;
| 78{
79 protected:
80
81 uint32_t imm;
|
69 uint32_t rotate;
| |
70 uint32_t rotated_imm;
71 uint32_t rotated_carry;
72
73 /// Constructor
| 82 uint32_t rotated_imm;
83 uint32_t rotated_carry;
84
85 /// Constructor
|
| 86 PredImmOpBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
87 PredOp(mnem, _machInst, __opClass),
88 imm(machInst.imm), rotated_imm(0), rotated_carry(0)
89 {
90 }
91
92 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
93};
94
95/**
96 * Base class for regular predicated immediate operations.
97 */
98class PredImmOp : public PredImmOpBase
99{
100 protected:
101
102 uint32_t rotate;
103
104 /// Constructor
|
74 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
| 105 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
|
75 PredOp(mnem, _machInst, __opClass),
76 imm(machInst.imm), rotate(machInst.rotate << 1),
77 rotated_imm(0), rotated_carry(0)
| 106 PredImmOpBase(mnem, _machInst, __opClass),
107 rotate(machInst.rotate << 1)
|
78 {
79 rotated_imm = rotate_imm(imm, rotate);
80 if (rotate != 0)
| 108 {
109 rotated_imm = rotate_imm(imm, rotate);
110 if (rotate != 0)
|
81 rotated_carry = (rotated_imm >> 31) & 1;
| 111 rotated_carry = bits(rotated_imm, 31);
|
82 }
| 112 }
|
| 113};
|
83
| 114
|
84 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 115/**
116 * Base class for modified predicated immediate operations.
117 */
118class PredModImmOp : public PredImmOpBase
119{
120 protected:
121
122 uint8_t ctrlImm;
123 uint8_t dataImm;
124
125
126 /// Constructor
127 PredModImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
128 PredImmOpBase(mnem, _machInst, __opClass),
129 ctrlImm(bits(machInst.instBits, 26) << 3 |
130 bits(machInst.instBits, 14, 12)),
131 dataImm(bits(machInst.instBits, 7, 0))
132 {
133 rotated_imm = modified_imm(ctrlImm, dataImm);
134 rotated_carry = bits(rotated_imm, 31);
135 }
|
85};
86
87/**
88 * Base class for predicated integer operations.
89 */
90class PredIntOp : public PredOp
91{
92 protected:
93
94 uint32_t shift_size;
95 uint32_t shift;
96
97 /// Constructor
98 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
99 PredOp(mnem, _machInst, __opClass),
100 shift_size(machInst.shiftSize), shift(machInst.shift)
101 {
102 }
103
104 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
105};
106
107/**
108 * Base class for predicated macro-operations.
109 */
110class PredMacroOp : public PredOp
111{
112 protected:
113
114 uint32_t numMicroops;
115 StaticInstPtr * microOps;
116
117 /// Constructor
118 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
119 PredOp(mnem, _machInst, __opClass),
120 numMicroops(0)
121 {
122 // We rely on the subclasses of this object to handle the
123 // initialization of the micro-operations, since they are
124 // all of variable length
125 flags[IsMacroop] = true;
126 }
127
128 ~PredMacroOp()
129 {
130 if (numMicroops)
131 delete [] microOps;
132 }
133
134 StaticInstPtr
135 fetchMicroop(MicroPC microPC)
136 {
137 assert(microPC < numMicroops);
138 return microOps[microPC];
139 }
140
141 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
142};
143
144/**
145 * Base class for predicated micro-operations.
146 */
147class PredMicroop : public PredOp
148{
149 /// Constructor
150 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
151 PredOp(mnem, _machInst, __opClass)
152 {
153 flags[IsMicroop] = true;
154 }
155};
156}
157
158#endif //__ARCH_ARM_INSTS_PREDINST_HH__
| 136};
137
138/**
139 * Base class for predicated integer operations.
140 */
141class PredIntOp : public PredOp
142{
143 protected:
144
145 uint32_t shift_size;
146 uint32_t shift;
147
148 /// Constructor
149 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
150 PredOp(mnem, _machInst, __opClass),
151 shift_size(machInst.shiftSize), shift(machInst.shift)
152 {
153 }
154
155 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
156};
157
158/**
159 * Base class for predicated macro-operations.
160 */
161class PredMacroOp : public PredOp
162{
163 protected:
164
165 uint32_t numMicroops;
166 StaticInstPtr * microOps;
167
168 /// Constructor
169 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
170 PredOp(mnem, _machInst, __opClass),
171 numMicroops(0)
172 {
173 // We rely on the subclasses of this object to handle the
174 // initialization of the micro-operations, since they are
175 // all of variable length
176 flags[IsMacroop] = true;
177 }
178
179 ~PredMacroOp()
180 {
181 if (numMicroops)
182 delete [] microOps;
183 }
184
185 StaticInstPtr
186 fetchMicroop(MicroPC microPC)
187 {
188 assert(microPC < numMicroops);
189 return microOps[microPC];
190 }
191
192 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
193};
194
195/**
196 * Base class for predicated micro-operations.
197 */
198class PredMicroop : public PredOp
199{
200 /// Constructor
201 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
202 PredOp(mnem, _machInst, __opClass)
203 {
204 flags[IsMicroop] = true;
205 }
206};
207}
208
209#endif //__ARCH_ARM_INSTS_PREDINST_HH__
|