1/*
2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43#define __ARCH_ARM_INSTS_PREDINST_HH__
44
45#include "arch/arm/insts/static_inst.hh"
| 1/*
2 * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43#define __ARCH_ARM_INSTS_PREDINST_HH__
44
45#include "arch/arm/insts/static_inst.hh"
|
46#include "base/trace.hh"
47
48namespace ArmISA
49{
50static inline uint32_t
51rotate_imm(uint32_t immValue, uint32_t rotateValue)
52{
53 rotateValue &= 31;
54 return rotateValue == 0 ? immValue :
55 (immValue >> rotateValue) | (immValue << (32 - rotateValue));
56}
57
58static inline uint32_t
59modified_imm(uint8_t ctrlImm, uint8_t dataImm)
60{
61 uint32_t bigData = dataImm;
62 uint32_t bigCtrl = ctrlImm;
63 if (bigCtrl < 4) {
64 switch (bigCtrl) {
65 case 0:
66 return bigData;
67 case 1:
68 return bigData | (bigData << 16);
69 case 2:
70 return (bigData << 8) | (bigData << 24);
71 case 3:
72 return (bigData << 0) | (bigData << 8) |
73 (bigData << 16) | (bigData << 24);
74 }
75 }
76 bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
77 bigData |= (1 << 7);
78 return bigData << (32 - bigCtrl);
79}
80
81static inline uint64_t
82simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
83 bool isAarch64 = false)
84{
85 uint64_t bigData = data;
86 immValid = true;
87 switch (cmode) {
88 case 0x0:
89 case 0x1:
90 bigData = (bigData << 0) | (bigData << 32);
91 break;
92 case 0x2:
93 case 0x3:
94 bigData = (bigData << 8) | (bigData << 40);
95 break;
96 case 0x4:
97 case 0x5:
98 bigData = (bigData << 16) | (bigData << 48);
99 break;
100 case 0x6:
101 case 0x7:
102 bigData = (bigData << 24) | (bigData << 56);
103 break;
104 case 0x8:
105 case 0x9:
106 bigData = (bigData << 0) | (bigData << 16) |
107 (bigData << 32) | (bigData << 48);
108 break;
109 case 0xa:
110 case 0xb:
111 bigData = (bigData << 8) | (bigData << 24) |
112 (bigData << 40) | (bigData << 56);
113 break;
114 case 0xc:
115 bigData = (0xffULL << 0) | (bigData << 8) |
116 (0xffULL << 32) | (bigData << 40);
117 break;
118 case 0xd:
119 bigData = (0xffffULL << 0) | (bigData << 16) |
120 (0xffffULL << 32) | (bigData << 48);
121 break;
122 case 0xe:
123 if (op) {
124 bigData = 0;
125 for (int i = 7; i >= 0; i--) {
126 if (bits(data, i)) {
127 bigData |= (ULL(0xFF) << (i * 8));
128 }
129 }
130 } else {
131 bigData = (bigData << 0) | (bigData << 8) |
132 (bigData << 16) | (bigData << 24) |
133 (bigData << 32) | (bigData << 40) |
134 (bigData << 48) | (bigData << 56);
135 }
136 break;
137 case 0xf:
138 {
139 uint64_t bVal = 0;
140 if (!op) {
141 bVal = bits(bigData, 6) ? (0x1F) : (0x20);
142 bigData = (bits(bigData, 5, 0) << 19) |
143 (bVal << 25) | (bits(bigData, 7) << 31);
144 bigData |= (bigData << 32);
145 break;
146 } else if (isAarch64) {
147 bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
148 bigData = (bits(bigData, 5, 0) << 48) |
149 (bVal << 54) | (bits(bigData, 7) << 63);
150 break;
151 }
152 }
153 M5_FALLTHROUGH;
154 default:
155 immValid = false;
156 break;
157 }
158 return bigData;
159}
160
161/** Floating point data types. */
162enum class FpDataType { Fp16, Fp32, Fp64 };
163
164static inline uint64_t
165vfp_modified_imm(uint8_t data, FpDataType dtype)
166{
167 uint64_t bigData = data;
168 uint64_t repData;
169 switch (dtype) {
170 case FpDataType::Fp16:
171 repData = bits(data, 6) ? 0x3 : 0;
172 bigData = (bits(bigData, 5, 0) << 6) |
173 (repData << 12) | (bits(~bigData, 6) << 14) |
174 (bits(bigData, 7) << 15);
175 break;
176 case FpDataType::Fp32:
177 repData = bits(data, 6) ? 0x1F : 0;
178 bigData = (bits(bigData, 5, 0) << 19) |
179 (repData << 25) | (bits(~bigData, 6) << 30) |
180 (bits(bigData, 7) << 31);
181 break;
182 case FpDataType::Fp64:
183 repData = bits(data, 6) ? 0xFF : 0;
184 bigData = (bits(bigData, 5, 0) << 48) |
185 (repData << 54) | (bits(~bigData, 6) << 62) |
186 (bits(bigData, 7) << 63);
187 break;
188 default:
| 47#include "base/trace.hh"
48
49namespace ArmISA
50{
51static inline uint32_t
52rotate_imm(uint32_t immValue, uint32_t rotateValue)
53{
54 rotateValue &= 31;
55 return rotateValue == 0 ? immValue :
56 (immValue >> rotateValue) | (immValue << (32 - rotateValue));
57}
58
59static inline uint32_t
60modified_imm(uint8_t ctrlImm, uint8_t dataImm)
61{
62 uint32_t bigData = dataImm;
63 uint32_t bigCtrl = ctrlImm;
64 if (bigCtrl < 4) {
65 switch (bigCtrl) {
66 case 0:
67 return bigData;
68 case 1:
69 return bigData | (bigData << 16);
70 case 2:
71 return (bigData << 8) | (bigData << 24);
72 case 3:
73 return (bigData << 0) | (bigData << 8) |
74 (bigData << 16) | (bigData << 24);
75 }
76 }
77 bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
78 bigData |= (1 << 7);
79 return bigData << (32 - bigCtrl);
80}
81
82static inline uint64_t
83simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
84 bool isAarch64 = false)
85{
86 uint64_t bigData = data;
87 immValid = true;
88 switch (cmode) {
89 case 0x0:
90 case 0x1:
91 bigData = (bigData << 0) | (bigData << 32);
92 break;
93 case 0x2:
94 case 0x3:
95 bigData = (bigData << 8) | (bigData << 40);
96 break;
97 case 0x4:
98 case 0x5:
99 bigData = (bigData << 16) | (bigData << 48);
100 break;
101 case 0x6:
102 case 0x7:
103 bigData = (bigData << 24) | (bigData << 56);
104 break;
105 case 0x8:
106 case 0x9:
107 bigData = (bigData << 0) | (bigData << 16) |
108 (bigData << 32) | (bigData << 48);
109 break;
110 case 0xa:
111 case 0xb:
112 bigData = (bigData << 8) | (bigData << 24) |
113 (bigData << 40) | (bigData << 56);
114 break;
115 case 0xc:
116 bigData = (0xffULL << 0) | (bigData << 8) |
117 (0xffULL << 32) | (bigData << 40);
118 break;
119 case 0xd:
120 bigData = (0xffffULL << 0) | (bigData << 16) |
121 (0xffffULL << 32) | (bigData << 48);
122 break;
123 case 0xe:
124 if (op) {
125 bigData = 0;
126 for (int i = 7; i >= 0; i--) {
127 if (bits(data, i)) {
128 bigData |= (ULL(0xFF) << (i * 8));
129 }
130 }
131 } else {
132 bigData = (bigData << 0) | (bigData << 8) |
133 (bigData << 16) | (bigData << 24) |
134 (bigData << 32) | (bigData << 40) |
135 (bigData << 48) | (bigData << 56);
136 }
137 break;
138 case 0xf:
139 {
140 uint64_t bVal = 0;
141 if (!op) {
142 bVal = bits(bigData, 6) ? (0x1F) : (0x20);
143 bigData = (bits(bigData, 5, 0) << 19) |
144 (bVal << 25) | (bits(bigData, 7) << 31);
145 bigData |= (bigData << 32);
146 break;
147 } else if (isAarch64) {
148 bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
149 bigData = (bits(bigData, 5, 0) << 48) |
150 (bVal << 54) | (bits(bigData, 7) << 63);
151 break;
152 }
153 }
154 M5_FALLTHROUGH;
155 default:
156 immValid = false;
157 break;
158 }
159 return bigData;
160}
161
162/** Floating point data types. */
163enum class FpDataType { Fp16, Fp32, Fp64 };
164
165static inline uint64_t
166vfp_modified_imm(uint8_t data, FpDataType dtype)
167{
168 uint64_t bigData = data;
169 uint64_t repData;
170 switch (dtype) {
171 case FpDataType::Fp16:
172 repData = bits(data, 6) ? 0x3 : 0;
173 bigData = (bits(bigData, 5, 0) << 6) |
174 (repData << 12) | (bits(~bigData, 6) << 14) |
175 (bits(bigData, 7) << 15);
176 break;
177 case FpDataType::Fp32:
178 repData = bits(data, 6) ? 0x1F : 0;
179 bigData = (bits(bigData, 5, 0) << 19) |
180 (repData << 25) | (bits(~bigData, 6) << 30) |
181 (bits(bigData, 7) << 31);
182 break;
183 case FpDataType::Fp64:
184 repData = bits(data, 6) ? 0xFF : 0;
185 bigData = (bits(bigData, 5, 0) << 48) |
186 (repData << 54) | (bits(~bigData, 6) << 62) |
187 (bits(bigData, 7) << 63);
188 break;
189 default:
|
190 }
191 return bigData;
192}
193
194static inline FpDataType
195decode_fp_data_type(uint8_t encoding)
196{
197 switch (encoding) {
198 case 1: return FpDataType::Fp16;
199 case 2: return FpDataType::Fp32;
200 case 3: return FpDataType::Fp64;
201 default:
202 panic(
203 "Invalid floating point data type in VFP/SIMD or SVE instruction");
204 }
205}
206
207/**
208 * Base class for predicated integer operations.
209 */
210class PredOp : public ArmStaticInst
211{
212 protected:
213
214 ConditionCode condCode;
215
216 /// Constructor
217 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
218 ArmStaticInst(mnem, _machInst, __opClass)
219 {
220 if (machInst.aarch64)
221 condCode = COND_UC;
222 else if (machInst.itstateMask)
223 condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
224 else
225 condCode = (ConditionCode)(unsigned)machInst.condCode;
226 }
227};
228
229/**
230 * Base class for predicated immediate operations.
231 */
232class PredImmOp : public PredOp
233{
234 protected:
235
236 uint32_t imm;
237 uint32_t rotated_imm;
238 uint32_t rotated_carry;
239 uint32_t rotate;
240
241 /// Constructor
242 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
243 PredOp(mnem, _machInst, __opClass),
244 imm(machInst.imm), rotated_imm(0), rotated_carry(0),
245 rotate(machInst.rotate << 1)
246 {
247 rotated_imm = rotate_imm(imm, rotate);
248 if (rotate != 0)
249 rotated_carry = bits(rotated_imm, 31);
250 }
251
252 std::string generateDisassembly(
253 Addr pc, const SymbolTable *symtab) const override;
254};
255
256/**
257 * Base class for predicated integer operations.
258 */
259class PredIntOp : public PredOp
260{
261 protected:
262
263 uint32_t shift_size;
264 uint32_t shift;
265
266 /// Constructor
267 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
268 PredOp(mnem, _machInst, __opClass),
269 shift_size(machInst.shiftSize), shift(machInst.shift)
270 {
271 }
272
273 std::string generateDisassembly(
274 Addr pc, const SymbolTable *symtab) const override;
275};
276
277class DataImmOp : public PredOp
278{
279 protected:
280 IntRegIndex dest, op1;
281 uint32_t imm;
282 // Whether the carry flag should be modified if that's an option for
283 // this instruction.
284 bool rotC;
285
286 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
287 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
288 PredOp(mnem, _machInst, __opClass),
289 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
290 {}
291
292 std::string generateDisassembly(
293 Addr pc, const SymbolTable *symtab) const override;
294};
295
296class DataRegOp : public PredOp
297{
298 protected:
299 IntRegIndex dest, op1, op2;
300 int32_t shiftAmt;
301 ArmShiftType shiftType;
302
303 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
304 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
305 int32_t _shiftAmt, ArmShiftType _shiftType) :
306 PredOp(mnem, _machInst, __opClass),
307 dest(_dest), op1(_op1), op2(_op2),
308 shiftAmt(_shiftAmt), shiftType(_shiftType)
309 {}
310
311 std::string generateDisassembly(
312 Addr pc, const SymbolTable *symtab) const override;
313};
314
315class DataRegRegOp : public PredOp
316{
317 protected:
318 IntRegIndex dest, op1, op2, shift;
319 ArmShiftType shiftType;
320
321 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
322 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
323 IntRegIndex _shift, ArmShiftType _shiftType) :
324 PredOp(mnem, _machInst, __opClass),
325 dest(_dest), op1(_op1), op2(_op2), shift(_shift),
326 shiftType(_shiftType)
327 {}
328
329 std::string generateDisassembly(
330 Addr pc, const SymbolTable *symtab) const override;
331};
332
333/**
334 * Base class for predicated macro-operations.
335 */
336class PredMacroOp : public PredOp
337{
338 protected:
339
340 uint32_t numMicroops;
341 StaticInstPtr * microOps;
342
343 /// Constructor
344 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
345 PredOp(mnem, _machInst, __opClass),
346 numMicroops(0), microOps(nullptr)
347 {
348 // We rely on the subclasses of this object to handle the
349 // initialization of the micro-operations, since they are
350 // all of variable length
351 flags[IsMacroop] = true;
352 }
353
354 ~PredMacroOp()
355 {
356 if (numMicroops)
357 delete [] microOps;
358 }
359
360 StaticInstPtr
361 fetchMicroop(MicroPC microPC) const override
362 {
363 assert(microPC < numMicroops);
364 return microOps[microPC];
365 }
366
367 Fault
368 execute(ExecContext *, Trace::InstRecord *) const override
369 {
370 panic("Execute method called when it shouldn't!");
371 }
372
373 std::string generateDisassembly(
374 Addr pc, const SymbolTable *symtab) const override;
375};
376
377/**
378 * Base class for predicated micro-operations.
379 */
380class PredMicroop : public PredOp
381{
382 /// Constructor
383 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
384 PredOp(mnem, _machInst, __opClass)
385 {
386 flags[IsMicroop] = true;
387 }
388
389 void
390 advancePC(PCState &pcState) const
391 {
392 if (flags[IsLastMicroop])
393 pcState.uEnd();
394 else
395 pcState.uAdvance();
396 }
397};
398}
399
400#endif //__ARCH_ARM_INSTS_PREDINST_HH__
| 191 }
192 return bigData;
193}
194
195static inline FpDataType
196decode_fp_data_type(uint8_t encoding)
197{
198 switch (encoding) {
199 case 1: return FpDataType::Fp16;
200 case 2: return FpDataType::Fp32;
201 case 3: return FpDataType::Fp64;
202 default:
203 panic(
204 "Invalid floating point data type in VFP/SIMD or SVE instruction");
205 }
206}
207
208/**
209 * Base class for predicated integer operations.
210 */
211class PredOp : public ArmStaticInst
212{
213 protected:
214
215 ConditionCode condCode;
216
217 /// Constructor
218 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
219 ArmStaticInst(mnem, _machInst, __opClass)
220 {
221 if (machInst.aarch64)
222 condCode = COND_UC;
223 else if (machInst.itstateMask)
224 condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
225 else
226 condCode = (ConditionCode)(unsigned)machInst.condCode;
227 }
228};
229
230/**
231 * Base class for predicated immediate operations.
232 */
233class PredImmOp : public PredOp
234{
235 protected:
236
237 uint32_t imm;
238 uint32_t rotated_imm;
239 uint32_t rotated_carry;
240 uint32_t rotate;
241
242 /// Constructor
243 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
244 PredOp(mnem, _machInst, __opClass),
245 imm(machInst.imm), rotated_imm(0), rotated_carry(0),
246 rotate(machInst.rotate << 1)
247 {
248 rotated_imm = rotate_imm(imm, rotate);
249 if (rotate != 0)
250 rotated_carry = bits(rotated_imm, 31);
251 }
252
253 std::string generateDisassembly(
254 Addr pc, const SymbolTable *symtab) const override;
255};
256
257/**
258 * Base class for predicated integer operations.
259 */
260class PredIntOp : public PredOp
261{
262 protected:
263
264 uint32_t shift_size;
265 uint32_t shift;
266
267 /// Constructor
268 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
269 PredOp(mnem, _machInst, __opClass),
270 shift_size(machInst.shiftSize), shift(machInst.shift)
271 {
272 }
273
274 std::string generateDisassembly(
275 Addr pc, const SymbolTable *symtab) const override;
276};
277
278class DataImmOp : public PredOp
279{
280 protected:
281 IntRegIndex dest, op1;
282 uint32_t imm;
283 // Whether the carry flag should be modified if that's an option for
284 // this instruction.
285 bool rotC;
286
287 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
288 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
289 PredOp(mnem, _machInst, __opClass),
290 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
291 {}
292
293 std::string generateDisassembly(
294 Addr pc, const SymbolTable *symtab) const override;
295};
296
297class DataRegOp : public PredOp
298{
299 protected:
300 IntRegIndex dest, op1, op2;
301 int32_t shiftAmt;
302 ArmShiftType shiftType;
303
304 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
305 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
306 int32_t _shiftAmt, ArmShiftType _shiftType) :
307 PredOp(mnem, _machInst, __opClass),
308 dest(_dest), op1(_op1), op2(_op2),
309 shiftAmt(_shiftAmt), shiftType(_shiftType)
310 {}
311
312 std::string generateDisassembly(
313 Addr pc, const SymbolTable *symtab) const override;
314};
315
316class DataRegRegOp : public PredOp
317{
318 protected:
319 IntRegIndex dest, op1, op2, shift;
320 ArmShiftType shiftType;
321
322 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
323 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
324 IntRegIndex _shift, ArmShiftType _shiftType) :
325 PredOp(mnem, _machInst, __opClass),
326 dest(_dest), op1(_op1), op2(_op2), shift(_shift),
327 shiftType(_shiftType)
328 {}
329
330 std::string generateDisassembly(
331 Addr pc, const SymbolTable *symtab) const override;
332};
333
334/**
335 * Base class for predicated macro-operations.
336 */
337class PredMacroOp : public PredOp
338{
339 protected:
340
341 uint32_t numMicroops;
342 StaticInstPtr * microOps;
343
344 /// Constructor
345 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
346 PredOp(mnem, _machInst, __opClass),
347 numMicroops(0), microOps(nullptr)
348 {
349 // We rely on the subclasses of this object to handle the
350 // initialization of the micro-operations, since they are
351 // all of variable length
352 flags[IsMacroop] = true;
353 }
354
355 ~PredMacroOp()
356 {
357 if (numMicroops)
358 delete [] microOps;
359 }
360
361 StaticInstPtr
362 fetchMicroop(MicroPC microPC) const override
363 {
364 assert(microPC < numMicroops);
365 return microOps[microPC];
366 }
367
368 Fault
369 execute(ExecContext *, Trace::InstRecord *) const override
370 {
371 panic("Execute method called when it shouldn't!");
372 }
373
374 std::string generateDisassembly(
375 Addr pc, const SymbolTable *symtab) const override;
376};
377
378/**
379 * Base class for predicated micro-operations.
380 */
381class PredMicroop : public PredOp
382{
383 /// Constructor
384 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
385 PredOp(mnem, _machInst, __opClass)
386 {
387 flags[IsMicroop] = true;
388 }
389
390 void
391 advancePC(PCState &pcState) const
392 {
393 if (flags[IsLastMicroop])
394 pcState.uEnd();
395 else
396 pcState.uAdvance();
397 }
398};
399}
400
401#endif //__ARCH_ARM_INSTS_PREDINST_HH__
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