1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43#define __ARCH_ARM_INSTS_PREDINST_HH__
44
45#include "arch/arm/insts/static_inst.hh"
46#include "base/trace.hh"
47
48namespace ArmISA
49{
50static inline uint32_t
51rotate_imm(uint32_t immValue, uint32_t rotateValue)
52{
53 rotateValue &= 31;
54 return rotateValue == 0 ? immValue :
55 (immValue >> rotateValue) | (immValue << (32 - rotateValue));
56}
57
58static inline uint32_t
59modified_imm(uint8_t ctrlImm, uint8_t dataImm)
60{
61 uint32_t bigData = dataImm;
62 uint32_t bigCtrl = ctrlImm;
63 if (bigCtrl < 4) {
64 switch (bigCtrl) {
65 case 0:
66 return bigData;
67 case 1:
68 return bigData | (bigData << 16);
69 case 2:
70 return (bigData << 8) | (bigData << 24);
71 case 3:
72 return (bigData << 0) | (bigData << 8) |
73 (bigData << 16) | (bigData << 24);
74 }
75 }
76 bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
77 bigData |= (1 << 7);
78 return bigData << (32 - bigCtrl);
79}
80
81static inline uint64_t
82simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
83 bool isAarch64 = false)
84{
85 uint64_t bigData = data;
86 immValid = true;
87 switch (cmode) {
88 case 0x0:
89 case 0x1:
90 bigData = (bigData << 0) | (bigData << 32);
91 break;
92 case 0x2:
93 case 0x3:
94 bigData = (bigData << 8) | (bigData << 40);
95 break;
96 case 0x4:
97 case 0x5:
98 bigData = (bigData << 16) | (bigData << 48);
99 break;
100 case 0x6:
101 case 0x7:
102 bigData = (bigData << 24) | (bigData << 56);
103 break;
104 case 0x8:
105 case 0x9:
106 bigData = (bigData << 0) | (bigData << 16) |
107 (bigData << 32) | (bigData << 48);
108 break;
109 case 0xa:
110 case 0xb:
111 bigData = (bigData << 8) | (bigData << 24) |
112 (bigData << 40) | (bigData << 56);
113 break;
114 case 0xc:
115 bigData = (0xffULL << 0) | (bigData << 8) |
116 (0xffULL << 32) | (bigData << 40);
117 break;
118 case 0xd:
119 bigData = (0xffffULL << 0) | (bigData << 16) |
120 (0xffffULL << 32) | (bigData << 48);
121 break;
122 case 0xe:
123 if (op) {
124 bigData = 0;
125 for (int i = 7; i >= 0; i--) {
126 if (bits(data, i)) {
127 bigData |= (ULL(0xFF) << (i * 8));
128 }
129 }
130 } else {
131 bigData = (bigData << 0) | (bigData << 8) |
132 (bigData << 16) | (bigData << 24) |
133 (bigData << 32) | (bigData << 40) |
134 (bigData << 48) | (bigData << 56);
135 }
136 break;
137 case 0xf:
138 {
139 uint64_t bVal = 0;
140 if (!op) {
141 bVal = bits(bigData, 6) ? (0x1F) : (0x20);
142 bigData = (bits(bigData, 5, 0) << 19) |
143 (bVal << 25) | (bits(bigData, 7) << 31);
144 bigData |= (bigData << 32);
145 break;
146 } else if (isAarch64) {
147 bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
148 bigData = (bits(bigData, 5, 0) << 48) |
149 (bVal << 54) | (bits(bigData, 7) << 63);
150 break;
151 }
152 }
153 M5_FALLTHROUGH;
154 default:
155 immValid = false;
156 break;
157 }
158 return bigData;
159}
160
161static inline uint64_t
162vfp_modified_imm(uint8_t data, bool wide)
163{
164 uint64_t bigData = data;
165 uint64_t repData;
166 if (wide) {
167 repData = bits(data, 6) ? 0xFF : 0;
168 bigData = (bits(bigData, 5, 0) << 48) |
169 (repData << 54) | (bits(~bigData, 6) << 62) |
170 (bits(bigData, 7) << 63);
171 } else {
172 repData = bits(data, 6) ? 0x1F : 0;
173 bigData = (bits(bigData, 5, 0) << 19) |
174 (repData << 25) | (bits(~bigData, 6) << 30) |
175 (bits(bigData, 7) << 31);
176 }
177 return bigData;
178}
179
180
181/**
182 * Base class for predicated integer operations.
183 */
184class PredOp : public ArmStaticInst
185{
186 protected:
187
188 ConditionCode condCode;
189
190 /// Constructor
191 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
192 ArmStaticInst(mnem, _machInst, __opClass)
193 {
194 if (machInst.aarch64)
195 condCode = COND_UC;
196 else if (machInst.itstateMask)
197 condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
198 else
199 condCode = (ConditionCode)(unsigned)machInst.condCode;
200 }
201};
202
203/**
204 * Base class for predicated immediate operations.
205 */
206class PredImmOp : public PredOp
207{
208 protected:
209
210 uint32_t imm;
211 uint32_t rotated_imm;
212 uint32_t rotated_carry;
213 uint32_t rotate;
214
215 /// Constructor
216 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
217 PredOp(mnem, _machInst, __opClass),
218 imm(machInst.imm), rotated_imm(0), rotated_carry(0),
219 rotate(machInst.rotate << 1)
220 {
221 rotated_imm = rotate_imm(imm, rotate);
222 if (rotate != 0)
223 rotated_carry = bits(rotated_imm, 31);
224 }
225
| 1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43#define __ARCH_ARM_INSTS_PREDINST_HH__
44
45#include "arch/arm/insts/static_inst.hh"
46#include "base/trace.hh"
47
48namespace ArmISA
49{
50static inline uint32_t
51rotate_imm(uint32_t immValue, uint32_t rotateValue)
52{
53 rotateValue &= 31;
54 return rotateValue == 0 ? immValue :
55 (immValue >> rotateValue) | (immValue << (32 - rotateValue));
56}
57
58static inline uint32_t
59modified_imm(uint8_t ctrlImm, uint8_t dataImm)
60{
61 uint32_t bigData = dataImm;
62 uint32_t bigCtrl = ctrlImm;
63 if (bigCtrl < 4) {
64 switch (bigCtrl) {
65 case 0:
66 return bigData;
67 case 1:
68 return bigData | (bigData << 16);
69 case 2:
70 return (bigData << 8) | (bigData << 24);
71 case 3:
72 return (bigData << 0) | (bigData << 8) |
73 (bigData << 16) | (bigData << 24);
74 }
75 }
76 bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
77 bigData |= (1 << 7);
78 return bigData << (32 - bigCtrl);
79}
80
81static inline uint64_t
82simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
83 bool isAarch64 = false)
84{
85 uint64_t bigData = data;
86 immValid = true;
87 switch (cmode) {
88 case 0x0:
89 case 0x1:
90 bigData = (bigData << 0) | (bigData << 32);
91 break;
92 case 0x2:
93 case 0x3:
94 bigData = (bigData << 8) | (bigData << 40);
95 break;
96 case 0x4:
97 case 0x5:
98 bigData = (bigData << 16) | (bigData << 48);
99 break;
100 case 0x6:
101 case 0x7:
102 bigData = (bigData << 24) | (bigData << 56);
103 break;
104 case 0x8:
105 case 0x9:
106 bigData = (bigData << 0) | (bigData << 16) |
107 (bigData << 32) | (bigData << 48);
108 break;
109 case 0xa:
110 case 0xb:
111 bigData = (bigData << 8) | (bigData << 24) |
112 (bigData << 40) | (bigData << 56);
113 break;
114 case 0xc:
115 bigData = (0xffULL << 0) | (bigData << 8) |
116 (0xffULL << 32) | (bigData << 40);
117 break;
118 case 0xd:
119 bigData = (0xffffULL << 0) | (bigData << 16) |
120 (0xffffULL << 32) | (bigData << 48);
121 break;
122 case 0xe:
123 if (op) {
124 bigData = 0;
125 for (int i = 7; i >= 0; i--) {
126 if (bits(data, i)) {
127 bigData |= (ULL(0xFF) << (i * 8));
128 }
129 }
130 } else {
131 bigData = (bigData << 0) | (bigData << 8) |
132 (bigData << 16) | (bigData << 24) |
133 (bigData << 32) | (bigData << 40) |
134 (bigData << 48) | (bigData << 56);
135 }
136 break;
137 case 0xf:
138 {
139 uint64_t bVal = 0;
140 if (!op) {
141 bVal = bits(bigData, 6) ? (0x1F) : (0x20);
142 bigData = (bits(bigData, 5, 0) << 19) |
143 (bVal << 25) | (bits(bigData, 7) << 31);
144 bigData |= (bigData << 32);
145 break;
146 } else if (isAarch64) {
147 bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
148 bigData = (bits(bigData, 5, 0) << 48) |
149 (bVal << 54) | (bits(bigData, 7) << 63);
150 break;
151 }
152 }
153 M5_FALLTHROUGH;
154 default:
155 immValid = false;
156 break;
157 }
158 return bigData;
159}
160
161static inline uint64_t
162vfp_modified_imm(uint8_t data, bool wide)
163{
164 uint64_t bigData = data;
165 uint64_t repData;
166 if (wide) {
167 repData = bits(data, 6) ? 0xFF : 0;
168 bigData = (bits(bigData, 5, 0) << 48) |
169 (repData << 54) | (bits(~bigData, 6) << 62) |
170 (bits(bigData, 7) << 63);
171 } else {
172 repData = bits(data, 6) ? 0x1F : 0;
173 bigData = (bits(bigData, 5, 0) << 19) |
174 (repData << 25) | (bits(~bigData, 6) << 30) |
175 (bits(bigData, 7) << 31);
176 }
177 return bigData;
178}
179
180
181/**
182 * Base class for predicated integer operations.
183 */
184class PredOp : public ArmStaticInst
185{
186 protected:
187
188 ConditionCode condCode;
189
190 /// Constructor
191 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
192 ArmStaticInst(mnem, _machInst, __opClass)
193 {
194 if (machInst.aarch64)
195 condCode = COND_UC;
196 else if (machInst.itstateMask)
197 condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
198 else
199 condCode = (ConditionCode)(unsigned)machInst.condCode;
200 }
201};
202
203/**
204 * Base class for predicated immediate operations.
205 */
206class PredImmOp : public PredOp
207{
208 protected:
209
210 uint32_t imm;
211 uint32_t rotated_imm;
212 uint32_t rotated_carry;
213 uint32_t rotate;
214
215 /// Constructor
216 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
217 PredOp(mnem, _machInst, __opClass),
218 imm(machInst.imm), rotated_imm(0), rotated_carry(0),
219 rotate(machInst.rotate << 1)
220 {
221 rotated_imm = rotate_imm(imm, rotate);
222 if (rotate != 0)
223 rotated_carry = bits(rotated_imm, 31);
224 }
225
|
226 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 226 std::string generateDisassembly(
227 Addr pc, const SymbolTable *symtab) const override;
|
227};
228
229/**
230 * Base class for predicated integer operations.
231 */
232class PredIntOp : public PredOp
233{
234 protected:
235
236 uint32_t shift_size;
237 uint32_t shift;
238
239 /// Constructor
240 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
241 PredOp(mnem, _machInst, __opClass),
242 shift_size(machInst.shiftSize), shift(machInst.shift)
243 {
244 }
245
| 228};
229
230/**
231 * Base class for predicated integer operations.
232 */
233class PredIntOp : public PredOp
234{
235 protected:
236
237 uint32_t shift_size;
238 uint32_t shift;
239
240 /// Constructor
241 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
242 PredOp(mnem, _machInst, __opClass),
243 shift_size(machInst.shiftSize), shift(machInst.shift)
244 {
245 }
246
|
246 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 247 std::string generateDisassembly(
248 Addr pc, const SymbolTable *symtab) const override;
|
247};
248
249class DataImmOp : public PredOp
250{
251 protected:
252 IntRegIndex dest, op1;
253 uint32_t imm;
254 // Whether the carry flag should be modified if that's an option for
255 // this instruction.
256 bool rotC;
257
258 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
259 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
260 PredOp(mnem, _machInst, __opClass),
261 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
262 {}
263
| 249};
250
251class DataImmOp : public PredOp
252{
253 protected:
254 IntRegIndex dest, op1;
255 uint32_t imm;
256 // Whether the carry flag should be modified if that's an option for
257 // this instruction.
258 bool rotC;
259
260 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
261 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
262 PredOp(mnem, _machInst, __opClass),
263 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
264 {}
265
|
264 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 266 std::string generateDisassembly(
267 Addr pc, const SymbolTable *symtab) const override;
|
265};
266
267class DataRegOp : public PredOp
268{
269 protected:
270 IntRegIndex dest, op1, op2;
271 int32_t shiftAmt;
272 ArmShiftType shiftType;
273
274 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
275 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
276 int32_t _shiftAmt, ArmShiftType _shiftType) :
277 PredOp(mnem, _machInst, __opClass),
278 dest(_dest), op1(_op1), op2(_op2),
279 shiftAmt(_shiftAmt), shiftType(_shiftType)
280 {}
281
| 268};
269
270class DataRegOp : public PredOp
271{
272 protected:
273 IntRegIndex dest, op1, op2;
274 int32_t shiftAmt;
275 ArmShiftType shiftType;
276
277 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
278 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
279 int32_t _shiftAmt, ArmShiftType _shiftType) :
280 PredOp(mnem, _machInst, __opClass),
281 dest(_dest), op1(_op1), op2(_op2),
282 shiftAmt(_shiftAmt), shiftType(_shiftType)
283 {}
284
|
282 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 285 std::string generateDisassembly(
286 Addr pc, const SymbolTable *symtab) const override;
|
283};
284
285class DataRegRegOp : public PredOp
286{
287 protected:
288 IntRegIndex dest, op1, op2, shift;
289 ArmShiftType shiftType;
290
291 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
292 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
293 IntRegIndex _shift, ArmShiftType _shiftType) :
294 PredOp(mnem, _machInst, __opClass),
295 dest(_dest), op1(_op1), op2(_op2), shift(_shift),
296 shiftType(_shiftType)
297 {}
298
| 287};
288
289class DataRegRegOp : public PredOp
290{
291 protected:
292 IntRegIndex dest, op1, op2, shift;
293 ArmShiftType shiftType;
294
295 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
296 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
297 IntRegIndex _shift, ArmShiftType _shiftType) :
298 PredOp(mnem, _machInst, __opClass),
299 dest(_dest), op1(_op1), op2(_op2), shift(_shift),
300 shiftType(_shiftType)
301 {}
302
|
299 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 303 std::string generateDisassembly(
304 Addr pc, const SymbolTable *symtab) const override;
|
300};
301
302/**
303 * Base class for predicated macro-operations.
304 */
305class PredMacroOp : public PredOp
306{
307 protected:
308
309 uint32_t numMicroops;
310 StaticInstPtr * microOps;
311
312 /// Constructor
313 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
314 PredOp(mnem, _machInst, __opClass),
315 numMicroops(0), microOps(nullptr)
316 {
317 // We rely on the subclasses of this object to handle the
318 // initialization of the micro-operations, since they are
319 // all of variable length
320 flags[IsMacroop] = true;
321 }
322
323 ~PredMacroOp()
324 {
325 if (numMicroops)
326 delete [] microOps;
327 }
328
329 StaticInstPtr
| 305};
306
307/**
308 * Base class for predicated macro-operations.
309 */
310class PredMacroOp : public PredOp
311{
312 protected:
313
314 uint32_t numMicroops;
315 StaticInstPtr * microOps;
316
317 /// Constructor
318 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
319 PredOp(mnem, _machInst, __opClass),
320 numMicroops(0), microOps(nullptr)
321 {
322 // We rely on the subclasses of this object to handle the
323 // initialization of the micro-operations, since they are
324 // all of variable length
325 flags[IsMacroop] = true;
326 }
327
328 ~PredMacroOp()
329 {
330 if (numMicroops)
331 delete [] microOps;
332 }
333
334 StaticInstPtr
|
330 fetchMicroop(MicroPC microPC) const
| 335 fetchMicroop(MicroPC microPC) const override
|
331 {
332 assert(microPC < numMicroops);
333 return microOps[microPC];
334 }
335
336 Fault
| 336 {
337 assert(microPC < numMicroops);
338 return microOps[microPC];
339 }
340
341 Fault
|
337 execute(ExecContext *, Trace::InstRecord *) const
| 342 execute(ExecContext *, Trace::InstRecord *) const override
|
338 {
339 panic("Execute method called when it shouldn't!");
340 }
341
| 343 {
344 panic("Execute method called when it shouldn't!");
345 }
346
|
342 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
| 347 std::string generateDisassembly(
348 Addr pc, const SymbolTable *symtab) const override;
|
343};
344
345/**
346 * Base class for predicated micro-operations.
347 */
348class PredMicroop : public PredOp
349{
350 /// Constructor
351 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
352 PredOp(mnem, _machInst, __opClass)
353 {
354 flags[IsMicroop] = true;
355 }
356
357 void
358 advancePC(PCState &pcState) const
359 {
360 if (flags[IsLastMicroop])
361 pcState.uEnd();
362 else
363 pcState.uAdvance();
364 }
365};
366}
367
368#endif //__ARCH_ARM_INSTS_PREDINST_HH__
| 349};
350
351/**
352 * Base class for predicated micro-operations.
353 */
354class PredMicroop : public PredOp
355{
356 /// Constructor
357 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
358 PredOp(mnem, _machInst, __opClass)
359 {
360 flags[IsMicroop] = true;
361 }
362
363 void
364 advancePC(PCState &pcState) const
365 {
366 if (flags[IsLastMicroop])
367 pcState.uEnd();
368 else
369 pcState.uAdvance();
370 }
371};
372}
373
374#endif //__ARCH_ARM_INSTS_PREDINST_HH__
|