1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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218 imm(machInst.imm), rotated_imm(0), rotated_carry(0),
219 rotate(machInst.rotate << 1)
220 {
221 rotated_imm = rotate_imm(imm, rotate);
222 if (rotate != 0)
223 rotated_carry = bits(rotated_imm, 31);
224 }
225
226 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
227};
228
229/**
230 * Base class for predicated integer operations.
231 */
232class PredIntOp : public PredOp
233{
234 protected:
235
236 uint32_t shift_size;
237 uint32_t shift;
238
239 /// Constructor
240 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
241 PredOp(mnem, _machInst, __opClass),
242 shift_size(machInst.shiftSize), shift(machInst.shift)
243 {
244 }
245
246 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
247};
248
249class DataImmOp : public PredOp
250{
251 protected:
252 IntRegIndex dest, op1;
253 uint32_t imm;
254 // Whether the carry flag should be modified if that's an option for
255 // this instruction.
256 bool rotC;
257
258 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
259 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
260 PredOp(mnem, _machInst, __opClass),
261 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
262 {}
263
264 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
265};
266
267class DataRegOp : public PredOp
268{
269 protected:
270 IntRegIndex dest, op1, op2;
271 int32_t shiftAmt;
272 ArmShiftType shiftType;
273
274 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
275 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
276 int32_t _shiftAmt, ArmShiftType _shiftType) :
277 PredOp(mnem, _machInst, __opClass),
278 dest(_dest), op1(_op1), op2(_op2),
279 shiftAmt(_shiftAmt), shiftType(_shiftType)
280 {}
281
282 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
283};
284
285class DataRegRegOp : public PredOp
286{
287 protected:
288 IntRegIndex dest, op1, op2, shift;
289 ArmShiftType shiftType;
290
291 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
292 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
293 IntRegIndex _shift, ArmShiftType _shiftType) :
294 PredOp(mnem, _machInst, __opClass),
295 dest(_dest), op1(_op1), op2(_op2), shift(_shift),
296 shiftType(_shiftType)
297 {}
298
299 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
300};
301
302/**
303 * Base class for predicated macro-operations.
304 */
305class PredMacroOp : public PredOp
306{
307 protected:

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322
323 ~PredMacroOp()
324 {
325 if (numMicroops)
326 delete [] microOps;
327 }
328
329 StaticInstPtr
330 fetchMicroop(MicroPC microPC) const
331 {
332 assert(microPC < numMicroops);
333 return microOps[microPC];
334 }
335
336 Fault
337 execute(ExecContext *, Trace::InstRecord *) const
338 {
339 panic("Execute method called when it shouldn't!");
340 }
341
342 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
343};
344
345/**
346 * Base class for predicated micro-operations.
347 */
348class PredMicroop : public PredOp
349{
350 /// Constructor

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