pred_inst.cc (6253:988a001820f8) pred_inst.cc (6262:43950710afdc)
1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright

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30#include "arch/arm/insts/pred_inst.hh"
31
32namespace ArmISA
33{
34std::string
35PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
36{
37 std::stringstream ss;
1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright

--- 21 unchanged lines hidden (view full) ---

30#include "arch/arm/insts/pred_inst.hh"
31
32namespace ArmISA
33{
34std::string
35PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
36{
37 std::stringstream ss;
38
39 ccprintf(ss, "%-10s ", mnemonic);
40
38 printMnemonic(ss);
41 if (_numDestRegs > 0) {
42 printReg(ss, _destRegIdx[0]);
43 }
44
45 ss << ", ";
46
47 if (_numSrcRegs > 0) {
48 printReg(ss, _srcRegIdx[0]);

--- 58 unchanged lines hidden --- 		39 if (_numDestRegs > 0) {
40 printReg(ss, _destRegIdx[0]);
41 }
42
43 ss << ", ";
44
45 if (_numSrcRegs > 0) {
46 printReg(ss, _srcRegIdx[0]);

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