1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43#include "arch/arm/insts/pred_inst.hh" 44 45namespace ArmISA 46{ 47std::string 48PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 49{ 50 std::stringstream ss; |
51 unsigned rotate = machInst.rotate * 2; 52 uint32_t imm = machInst.imm; 53 imm = (imm << (32 - rotate)) | (imm >> rotate); 54 printDataInst(ss, false, machInst.opcode4 == 0, machInst.sField, 55 (IntRegIndex)(uint32_t)machInst.rd, 56 (IntRegIndex)(uint32_t)machInst.rn, 57 (IntRegIndex)(uint32_t)machInst.rm, 58 (IntRegIndex)(uint32_t)machInst.rs, 59 machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift, 60 imm); |
61 return ss.str(); 62} 63 64std::string 65PredImmOpBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const 66{ 67 std::stringstream ss; |
68 unsigned rotate = machInst.rotate * 2; 69 uint32_t imm = machInst.imm; 70 imm = (imm << (32 - rotate)) | (imm >> rotate); 71 printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField, 72 (IntRegIndex)(uint32_t)machInst.rd, 73 (IntRegIndex)(uint32_t)machInst.rn, 74 (IntRegIndex)(uint32_t)machInst.rm, 75 (IntRegIndex)(uint32_t)machInst.rs, 76 machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift, 77 imm); |
78 return ss.str(); 79} 80 81std::string |
82DataImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 83{ 84 std::stringstream ss; 85 printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1, 86 INTREG_ZERO, INTREG_ZERO, 0, LSL, imm); 87 return ss.str(); 88} 89 90std::string 91DataRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 92{ 93 std::stringstream ss; 94 printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, 95 op2, INTREG_ZERO, shiftAmt, shiftType, 0); 96 return ss.str(); 97} 98 99std::string 100DataRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 101{ 102 std::stringstream ss; 103 printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1, 104 op2, shift, 0, shiftType, 0); 105 return ss.str(); 106} 107 108std::string |
109PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 110{ 111 std::stringstream ss; 112 113 ccprintf(ss, "%-10s ", mnemonic); 114 115 return ss.str(); 116} 117} |