1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#include "arch/arm/insts/pred_inst.hh" 44 45namespace ArmISA 46{ 47std::string 48PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 49{ 50 std::stringstream ss;
| 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42 43#include "arch/arm/insts/pred_inst.hh" 44 45namespace ArmISA 46{ 47std::string 48PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 49{ 50 std::stringstream ss;
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51 printDataInst(ss, false);
| 51 unsigned rotate = machInst.rotate * 2; 52 uint32_t imm = machInst.imm; 53 imm = (imm << (32 - rotate)) | (imm >> rotate); 54 printDataInst(ss, false, machInst.opcode4 == 0, machInst.sField, 55 (IntRegIndex)(uint32_t)machInst.rd, 56 (IntRegIndex)(uint32_t)machInst.rn, 57 (IntRegIndex)(uint32_t)machInst.rm, 58 (IntRegIndex)(uint32_t)machInst.rs, 59 machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift, 60 imm);
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52 return ss.str(); 53} 54 55std::string 56PredImmOpBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const 57{ 58 std::stringstream ss;
| 61 return ss.str(); 62} 63 64std::string 65PredImmOpBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const 66{ 67 std::stringstream ss;
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59 printDataInst(ss, true);
| 68 unsigned rotate = machInst.rotate * 2; 69 uint32_t imm = machInst.imm; 70 imm = (imm << (32 - rotate)) | (imm >> rotate); 71 printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField, 72 (IntRegIndex)(uint32_t)machInst.rd, 73 (IntRegIndex)(uint32_t)machInst.rn, 74 (IntRegIndex)(uint32_t)machInst.rm, 75 (IntRegIndex)(uint32_t)machInst.rs, 76 machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift, 77 imm);
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60 return ss.str(); 61} 62 63std::string
| 78 return ss.str(); 79} 80 81std::string
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| 82DataImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 83{ 84 std::stringstream ss; 85 printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1, 86 INTREG_ZERO, INTREG_ZERO, 0, LSL, imm); 87 return ss.str(); 88} 89 90std::string 91DataRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 92{ 93 std::stringstream ss; 94 printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, 95 op2, INTREG_ZERO, shiftAmt, shiftType, 0); 96 return ss.str(); 97} 98 99std::string 100DataRegRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 101{ 102 std::stringstream ss; 103 printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1, 104 op2, shift, 0, shiftType, 0); 105 return ss.str(); 106} 107 108std::string
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64PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 65{ 66 std::stringstream ss; 67 68 ccprintf(ss, "%-10s ", mnemonic); 69 70 return ss.str(); 71} 72}
| 109PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 110{ 111 std::stringstream ss; 112 113 ccprintf(ss, "%-10s ", mnemonic); 114 115 return ss.str(); 116} 117}
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