1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#include "arch/arm/insts/pred_inst.hh"
44
45namespace ArmISA
46{
47std::string
48PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
49{
50 std::stringstream ss;
51 printDataInst(ss, false);
52 return ss.str();
53}
54
55std::string
56PredImmOpBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
57{
58 std::stringstream ss;
59 printDataInst(ss, true);
60 return ss.str();
61}
62
63std::string
64PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
65{
66 std::stringstream ss;
67
68 ccprintf(ss, "%-10s ", mnemonic);
69
70 return ss.str();
71}
72}