1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright

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30#include "arch/arm/insts/pred_inst.hh"
31
32namespace ArmISA
33{
34std::string
35PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
36{
37 std::stringstream ss;
38 printDataInst(ss);
39 return ss.str();
40}
41
42std::string
43PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
44{
45 std::stringstream ss;
46
47 ccprintf(ss, "%-10s ", mnemonic);
48
49 return ss.str();
50}
51}