misc64.hh (12616:4b463b4dc098) | misc64.hh (13364:055bf0fa0f02) |
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1/* 2 * Copyright (c) 2011-2013,2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 92 unchanged lines hidden (view full) --- 101 UnknownOp64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 102 ArmStaticInst(mnem, _machInst, __opClass) 103 {} 104 105 std::string generateDisassembly( 106 Addr pc, const SymbolTable *symtab) const override; 107}; 108 | 1/* 2 * Copyright (c) 2011-2013,2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 92 unchanged lines hidden (view full) --- 101 UnknownOp64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 102 ArmStaticInst(mnem, _machInst, __opClass) 103 {} 104 105 std::string generateDisassembly( 106 Addr pc, const SymbolTable *symtab) const override; 107}; 108 |
109class MiscRegRegImmOp64 : public ArmStaticInst | 109/** 110 * This class is implementing the Base class for a generic AArch64 111 * instruction which is making use of system registers (MiscReg), like 112 * MSR,MRS,SYS. The common denominator or those instruction is the 113 * chance that the system register access is trapped to an upper 114 * Exception level. MiscRegOp64 is providing that feature. Other 115 * "pseudo" instructions, like access to implementation defined 116 * registers can inherit from this class to make use of the trapping 117 * functionalities even if there is no data movement between GPRs and 118 * system register. 119 */ 120class MiscRegOp64 : public ArmStaticInst |
110{ 111 protected: | 121{ 122 protected: |
123 bool miscRead; 124 125 MiscRegOp64(const char *mnem, ExtMachInst _machInst, 126 OpClass __opClass, bool misc_read) : 127 ArmStaticInst(mnem, _machInst, __opClass), 128 miscRead(misc_read) 129 {} 130 131 Fault trap(ThreadContext *tc, MiscRegIndex misc_reg, 132 ExceptionLevel el, uint32_t immediate) const; 133 private: 134 bool checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 135 ExceptionLevel el) const; 136 137 bool checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 138 ExceptionLevel el, bool *is_vfp_neon) const; 139 140 bool checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 141 ExceptionLevel el, bool *is_vfp_neon) const; 142 143}; 144 145class MiscRegRegImmOp64 : public MiscRegOp64 146{ 147 protected: |
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112 MiscRegIndex dest; 113 IntRegIndex op1; 114 uint32_t imm; 115 116 MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst, 117 OpClass __opClass, MiscRegIndex _dest, 118 IntRegIndex _op1, uint32_t _imm) : | 148 MiscRegIndex dest; 149 IntRegIndex op1; 150 uint32_t imm; 151 152 MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst, 153 OpClass __opClass, MiscRegIndex _dest, 154 IntRegIndex _op1, uint32_t _imm) : |
119 ArmStaticInst(mnem, _machInst, __opClass), | 155 MiscRegOp64(mnem, _machInst, __opClass, false), |
120 dest(_dest), op1(_op1), imm(_imm) 121 {} 122 123 std::string generateDisassembly( 124 Addr pc, const SymbolTable *symtab) const override; 125}; 126 | 156 dest(_dest), op1(_op1), imm(_imm) 157 {} 158 159 std::string generateDisassembly( 160 Addr pc, const SymbolTable *symtab) const override; 161}; 162 |
127class RegMiscRegImmOp64 : public ArmStaticInst | 163class RegMiscRegImmOp64 : public MiscRegOp64 |
128{ 129 protected: 130 IntRegIndex dest; 131 MiscRegIndex op1; 132 uint32_t imm; 133 134 RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst, 135 OpClass __opClass, IntRegIndex _dest, 136 MiscRegIndex _op1, uint32_t _imm) : | 164{ 165 protected: 166 IntRegIndex dest; 167 MiscRegIndex op1; 168 uint32_t imm; 169 170 RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst, 171 OpClass __opClass, IntRegIndex _dest, 172 MiscRegIndex _op1, uint32_t _imm) : |
137 ArmStaticInst(mnem, _machInst, __opClass), | 173 MiscRegOp64(mnem, _machInst, __opClass, true), |
138 dest(_dest), op1(_op1), imm(_imm) 139 {} 140 141 std::string generateDisassembly( 142 Addr pc, const SymbolTable *symtab) const override; 143}; 144 145#endif | 174 dest(_dest), op1(_op1), imm(_imm) 175 {} 176 177 std::string generateDisassembly( 178 Addr pc, const SymbolTable *symtab) const override; 179}; 180 181#endif |