1/* 2 * Copyright (c) 2011-2013,2017-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 38 unchanged lines hidden (view full) --- 47 protected: 48 uint64_t imm; 49 50 ImmOp64(const char *mnem, ExtMachInst _machInst, 51 OpClass __opClass, uint64_t _imm) : 52 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm) 53 {} 54 |
55 std::string generateDisassembly( 56 Addr pc, const SymbolTable *symtab) const override; |
57}; 58 59class RegRegImmImmOp64 : public ArmStaticInst 60{ 61 protected: 62 IntRegIndex dest; 63 IntRegIndex op1; 64 uint64_t imm1; 65 uint64_t imm2; 66 67 RegRegImmImmOp64(const char *mnem, ExtMachInst _machInst, 68 OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 69 uint64_t _imm1, uint64_t _imm2) : 70 ArmStaticInst(mnem, _machInst, __opClass), 71 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) 72 {} 73 |
74 std::string generateDisassembly( 75 Addr pc, const SymbolTable *symtab) const override; |
76}; 77 78class RegRegRegImmOp64 : public ArmStaticInst 79{ 80 protected: 81 IntRegIndex dest; 82 IntRegIndex op1; 83 IntRegIndex op2; 84 uint64_t imm; 85 86 RegRegRegImmOp64(const char *mnem, ExtMachInst _machInst, 87 OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 88 IntRegIndex _op2, uint64_t _imm) : 89 ArmStaticInst(mnem, _machInst, __opClass), 90 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 91 {} 92 |
93 std::string generateDisassembly( 94 Addr pc, const SymbolTable *symtab) const override; |
95}; 96 97class UnknownOp64 : public ArmStaticInst 98{ 99 protected: 100 101 UnknownOp64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 102 ArmStaticInst(mnem, _machInst, __opClass) 103 {} 104 |
105 std::string generateDisassembly( 106 Addr pc, const SymbolTable *symtab) const override; |
107}; 108 109class MiscRegRegImmOp64 : public ArmStaticInst 110{ 111 protected: 112 MiscRegIndex dest; 113 IntRegIndex op1; 114 uint32_t imm; 115 116 MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst, 117 OpClass __opClass, MiscRegIndex _dest, 118 IntRegIndex _op1, uint32_t _imm) : 119 ArmStaticInst(mnem, _machInst, __opClass), 120 dest(_dest), op1(_op1), imm(_imm) 121 {} 122 |
123 std::string generateDisassembly( 124 Addr pc, const SymbolTable *symtab) const override; |
125}; 126 127class RegMiscRegImmOp64 : public ArmStaticInst 128{ 129 protected: 130 IntRegIndex dest; 131 MiscRegIndex op1; 132 uint32_t imm; 133 134 RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst, 135 OpClass __opClass, IntRegIndex _dest, 136 MiscRegIndex _op1, uint32_t _imm) : 137 ArmStaticInst(mnem, _machInst, __opClass), 138 dest(_dest), op1(_op1), imm(_imm) 139 {} 140 |
141 std::string generateDisassembly( 142 Addr pc, const SymbolTable *symtab) const override; |
143}; 144 145#endif |