1/*
2 * Copyright (c) 2011-2013,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_ARM_INSTS_MISC64_HH__
41#define __ARCH_ARM_INSTS_MISC64_HH__
42
43#include "arch/arm/insts/static_inst.hh"
44
45class ImmOp64 : public ArmStaticInst
46{
47 protected:
48 uint64_t imm;
49
50 ImmOp64(const char *mnem, ExtMachInst _machInst,
51 OpClass __opClass, uint64_t _imm) :
52 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm)
53 {}
54
55 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
56};
57
58class RegRegImmImmOp64 : public ArmStaticInst
59{
60 protected:
61 IntRegIndex dest;
62 IntRegIndex op1;
63 uint64_t imm1;
64 uint64_t imm2;
65
66 RegRegImmImmOp64(const char *mnem, ExtMachInst _machInst,
67 OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
68 uint64_t _imm1, uint64_t _imm2) :
69 ArmStaticInst(mnem, _machInst, __opClass),
70 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
71 {}
72
73 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
74};
75
76class RegRegRegImmOp64 : public ArmStaticInst
77{
78 protected:
79 IntRegIndex dest;
80 IntRegIndex op1;
81 IntRegIndex op2;
82 uint64_t imm;
83
84 RegRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
85 OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
86 IntRegIndex _op2, uint64_t _imm) :
87 ArmStaticInst(mnem, _machInst, __opClass),
88 dest(_dest), op1(_op1), op2(_op2), imm(_imm)
89 {}
90
91 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
92};
93
94class UnknownOp64 : public ArmStaticInst
95{
96 protected:
97
98 UnknownOp64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
99 ArmStaticInst(mnem, _machInst, __opClass)
100 {}
101
102 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
103};
104
105class MiscRegRegImmOp64 : public ArmStaticInst
106{
107 protected:
108 MiscRegIndex dest;
109 IntRegIndex op1;
110 uint32_t imm;
111
112 MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
113 OpClass __opClass, MiscRegIndex _dest,
114 IntRegIndex _op1, uint32_t _imm) :
115 ArmStaticInst(mnem, _machInst, __opClass),
116 dest(_dest), op1(_op1), imm(_imm)
117 {}
118
119 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
120};
121
122class RegMiscRegImmOp64 : public ArmStaticInst
123{
124 protected:
125 IntRegIndex dest;
126 MiscRegIndex op1;
127 uint32_t imm;
128
129 RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
130 OpClass __opClass, IntRegIndex _dest,
131 MiscRegIndex _op1, uint32_t _imm) :
132 ArmStaticInst(mnem, _machInst, __opClass),
133 dest(_dest), op1(_op1), imm(_imm)
134 {}
135
136 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
137};
138
139#endif