1/*
2 * Copyright (c) 2011-2013,2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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101 UnknownOp64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
102 ArmStaticInst(mnem, _machInst, __opClass)
103 {}
104
105 std::string generateDisassembly(
106 Addr pc, const SymbolTable *symtab) const override;
107};
108
109class MiscRegRegImmOp64 : public ArmStaticInst
110{
111 protected:
112 MiscRegIndex dest;
113 IntRegIndex op1;
114 uint32_t imm;
115
116 MiscRegRegImmOp64(const char *mnem, ExtMachInst _machInst,
117 OpClass __opClass, MiscRegIndex _dest,
118 IntRegIndex _op1, uint32_t _imm) :
119 ArmStaticInst(mnem, _machInst, __opClass),
120 dest(_dest), op1(_op1), imm(_imm)
121 {}
122
123 std::string generateDisassembly(
124 Addr pc, const SymbolTable *symtab) const override;
125};
126
127class RegMiscRegImmOp64 : public ArmStaticInst
128{
129 protected:
130 IntRegIndex dest;
131 MiscRegIndex op1;
132 uint32_t imm;
133
134 RegMiscRegImmOp64(const char *mnem, ExtMachInst _machInst,
135 OpClass __opClass, IntRegIndex _dest,
136 MiscRegIndex _op1, uint32_t _imm) :
137 ArmStaticInst(mnem, _machInst, __opClass),
138 dest(_dest), op1(_op1), imm(_imm)
139 {}
140
141 std::string generateDisassembly(
142 Addr pc, const SymbolTable *symtab) const override;
143};
144
145#endif