misc.hh (7409:1ff897327905) misc.hh (10037:5cac77888310)
1/*
1/*
2 * Copyright (c) 2010 ARM Limited
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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89 MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
90 IntRegIndex _op1, uint8_t _byteMask) :
91 MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
92 {}
93
94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
95};
96
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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89 MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
90 IntRegIndex _op1, uint8_t _byteMask) :
91 MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
92 {}
93
94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
95};
96
97class MrrcOp : public PredOp
98{
99 protected:
100 IntRegIndex op1;
101 IntRegIndex dest;
102 IntRegIndex dest2;
103 uint32_t imm;
104
105 MrrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
106 IntRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2,
107 uint32_t _imm) :
108 PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
109 dest2(_dest2), imm(_imm)
110 {}
111
112 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
113};
114
115class McrrOp : public PredOp
116{
117 protected:
118 IntRegIndex op1;
119 IntRegIndex op2;
120 IntRegIndex dest;
121 uint32_t imm;
122
123 McrrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
124 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _dest,
125 uint32_t _imm) :
126 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
127 dest(_dest), imm(_imm)
128 {}
129
130 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
131};
132
97class ImmOp : public PredOp
98{
99 protected:
100 uint64_t imm;
101
102 ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
103 uint64_t _imm) :
104 PredOp(mnem, _machInst, __opClass), imm(_imm)

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215 uint64_t _imm) :
216 PredOp(mnem, _machInst, __opClass),
217 dest(_dest), op1(_op1), imm(_imm)
218 {}
219
220 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
221};
222
133class ImmOp : public PredOp
134{
135 protected:
136 uint64_t imm;
137
138 ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
139 uint64_t _imm) :
140 PredOp(mnem, _machInst, __opClass), imm(_imm)

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251 uint64_t _imm) :
252 PredOp(mnem, _machInst, __opClass),
253 dest(_dest), op1(_op1), imm(_imm)
254 {}
255
256 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
257};
258
259class RegImmImmOp : public PredOp
260{
261 protected:
262 IntRegIndex dest;
263 IntRegIndex op1;
264 uint64_t imm1;
265 uint64_t imm2;
266
267 RegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
268 IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2) :
269 PredOp(mnem, _machInst, __opClass),
270 dest(_dest), imm1(_imm1), imm2(_imm2)
271 {}
272
273 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
274};
275
223class RegRegImmImmOp : public PredOp
224{
225 protected:
226 IntRegIndex dest;
227 IntRegIndex op1;
228 uint64_t imm1;
229 uint64_t imm2;
230

--- 42 unchanged lines hidden --- 		276class RegRegImmImmOp : public PredOp
277{
278 protected:
279 IntRegIndex dest;
280 IntRegIndex op1;
281 uint64_t imm1;
282 uint64_t imm2;
283

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