misc.hh (7232:f633e1a3f644) misc.hh (7233:687fa9b9c2b5)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 110 unchanged lines hidden (view full) ---

119 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1) :
120 PredOp(mnem, _machInst, __opClass),
121 dest(_dest), imm(_imm), op1(_op1)
122 {}
123
124 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
125};
126
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 110 unchanged lines hidden (view full) ---

119 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1) :
120 PredOp(mnem, _machInst, __opClass),
121 dest(_dest), imm(_imm), op1(_op1)
122 {}
123
124 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
125};
126
127class RegRegRegImmOp : public PredOp
128{
129 protected:
130 IntRegIndex dest;
131 IntRegIndex op1;
132 IntRegIndex op2;
133 uint32_t imm;
134
135 RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
136 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
137 uint32_t _imm) :
138 PredOp(mnem, _machInst, __opClass),
139 dest(_dest), op1(_op1), op2(_op2), imm(_imm)
140 {}
141
142 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
143};
144
127class RegImmRegShiftOp : public PredOp
128{
129 protected:
130 IntRegIndex dest;
131 uint32_t imm;
132 IntRegIndex op1;
133 int32_t shiftAmt;
134 ArmShiftType shiftType;

--- 13 unchanged lines hidden --- 		145class RegImmRegShiftOp : public PredOp
146{
147 protected:
148 IntRegIndex dest;
149 uint32_t imm;
150 IntRegIndex op1;
151 int32_t shiftAmt;
152 ArmShiftType shiftType;

--- 13 unchanged lines hidden ---