misc.hh (7225:bf41a07cc7c0) misc.hh (7232:f633e1a3f644)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 94 unchanged lines hidden (view full) ---

103 RevOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
104 IntRegIndex _dest, IntRegIndex _op1) :
105 PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
106 {}
107
108 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
109};
110
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 94 unchanged lines hidden (view full) ---

103 RevOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
104 IntRegIndex _dest, IntRegIndex _op1) :
105 PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
106 {}
107
108 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
109};
110
111class SatOp : public PredOp
111class RegImmRegOp : public PredOp
112{
113 protected:
114 IntRegIndex dest;
112{
113 protected:
114 IntRegIndex dest;
115 uint32_t satImm;
115 uint32_t imm;
116 IntRegIndex op1;
117
116 IntRegIndex op1;
117
118 SatOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
119 IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1) :
118 RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
119 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1) :
120 PredOp(mnem, _machInst, __opClass),
120 PredOp(mnem, _machInst, __opClass),
121 dest(_dest), satImm(_satImm), op1(_op1)
121 dest(_dest), imm(_imm), op1(_op1)
122 {}
123
124 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
125};
126
122 {}
123
124 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
125};
126
127class SatShiftOp : public PredOp
127class RegImmRegShiftOp : public PredOp
128{
129 protected:
130 IntRegIndex dest;
128{
129 protected:
130 IntRegIndex dest;
131 uint32_t satImm;
131 uint32_t imm;
132 IntRegIndex op1;
133 int32_t shiftAmt;
134 ArmShiftType shiftType;
135
132 IntRegIndex op1;
133 int32_t shiftAmt;
134 ArmShiftType shiftType;
135
136 SatShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
137 IntRegIndex _dest, uint32_t _satImm, IntRegIndex _op1,
138 int32_t _shiftAmt, ArmShiftType _shiftType) :
136 RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
137 IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
138 int32_t _shiftAmt, ArmShiftType _shiftType) :
139 PredOp(mnem, _machInst, __opClass),
139 PredOp(mnem, _machInst, __opClass),
140 dest(_dest), satImm(_satImm), op1(_op1),
140 dest(_dest), imm(_imm), op1(_op1),
141 shiftAmt(_shiftAmt), shiftType(_shiftType)
142 {}
143
144 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
145};
146
147#endif
141 shiftAmt(_shiftAmt), shiftType(_shiftType)
142 {}
143
144 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
145};
146
147#endif