misc.hh (10418:7a76e13f0101) misc.hh (10420:cc13df09fa55)
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 83 unchanged lines hidden (view full) ---

92 {}
93
94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
95};
96
97class MrrcOp : public PredOp
98{
99 protected:
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 83 unchanged lines hidden (view full) ---

92 {}
93
94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
95};
96
97class MrrcOp : public PredOp
98{
99 protected:
100 IntRegIndex op1;
100 MiscRegIndex op1;
101 IntRegIndex dest;
102 IntRegIndex dest2;
103 uint32_t imm;
104
105 MrrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
101 IntRegIndex dest;
102 IntRegIndex dest2;
103 uint32_t imm;
104
105 MrrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
106 IntRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2,
106 MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2,
107 uint32_t _imm) :
108 PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
109 dest2(_dest2), imm(_imm)
110 {}
111
112 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
113};
114
115class McrrOp : public PredOp
116{
117 protected:
118 IntRegIndex op1;
119 IntRegIndex op2;
107 uint32_t _imm) :
108 PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
109 dest2(_dest2), imm(_imm)
110 {}
111
112 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
113};
114
115class McrrOp : public PredOp
116{
117 protected:
118 IntRegIndex op1;
119 IntRegIndex op2;
120 IntRegIndex dest;
120 MiscRegIndex dest;
121 uint32_t imm;
122
123 McrrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
121 uint32_t imm;
122
123 McrrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
124 IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _dest,
124 IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest,
125 uint32_t _imm) :
126 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
127 dest(_dest), imm(_imm)
128 {}
129
130 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
131};
132

--- 227 unchanged lines hidden --- 		125 uint32_t _imm) :
126 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
127 dest(_dest), imm(_imm)
128 {}
129
130 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
131};
132

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