1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 175 unchanged lines hidden (view full) --- 184 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) : 185 PredOp(mnem, _machInst, __opClass), 186 dest(_dest), op1(_op1), op2(_op2) 187 {} 188 189 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 190}; 191 |
192class RegRegImmOp : public PredOp 193{ 194 protected: 195 IntRegIndex dest; 196 IntRegIndex op1; 197 uint64_t imm; 198 199 RegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 200 IntRegIndex _dest, IntRegIndex _op1, 201 uint64_t _imm) : 202 PredOp(mnem, _machInst, __opClass), 203 dest(_dest), op1(_op1), imm(_imm) 204 {} 205 206 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 207}; 208 |
209class RegRegImmImmOp : public PredOp 210{ 211 protected: 212 IntRegIndex dest; 213 IntRegIndex op1; 214 uint64_t imm1; 215 uint64_t imm2; 216 --- 31 unchanged lines hidden --- |