1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 83 unchanged lines hidden (view full) --- 92 {} 93 94 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 95}; 96 97class ImmOp : public PredOp 98{ 99 protected: |
100 uint64_t imm; |
101 102 ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
103 uint64_t _imm) : |
104 PredOp(mnem, _machInst, __opClass), imm(_imm) 105 {} 106 107 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 108}; 109 110class RegRegOp : public PredOp 111{ --- 8 unchanged lines hidden (view full) --- 120 121 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 122}; 123 124class RegImmRegOp : public PredOp 125{ 126 protected: 127 IntRegIndex dest; |
128 uint64_t imm; |
129 IntRegIndex op1; 130 131 RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
132 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1) : |
133 PredOp(mnem, _machInst, __opClass), 134 dest(_dest), imm(_imm), op1(_op1) 135 {} 136 137 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 138}; 139 140class RegRegRegImmOp : public PredOp 141{ 142 protected: 143 IntRegIndex dest; 144 IntRegIndex op1; 145 IntRegIndex op2; |
146 uint64_t imm; |
147 148 RegRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 149 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, |
150 uint64_t _imm) : |
151 PredOp(mnem, _machInst, __opClass), 152 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 153 {} 154 155 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 156}; 157 158class RegRegRegRegOp : public PredOp --- 30 unchanged lines hidden (view full) --- 189 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 190}; 191 192class RegRegImmImmOp : public PredOp 193{ 194 protected: 195 IntRegIndex dest; 196 IntRegIndex op1; |
197 uint64_t imm1; 198 uint64_t imm2; |
199 200 RegRegImmImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 201 IntRegIndex _dest, IntRegIndex _op1, |
202 uint64_t _imm1, uint64_t _imm2) : |
203 PredOp(mnem, _machInst, __opClass), 204 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) 205 {} 206 207 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 208}; 209 210class RegImmRegShiftOp : public PredOp 211{ 212 protected: 213 IntRegIndex dest; |
214 uint64_t imm; |
215 IntRegIndex op1; 216 int32_t shiftAmt; 217 ArmShiftType shiftType; 218 219 RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, |
220 IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, |
221 int32_t _shiftAmt, ArmShiftType _shiftType) : 222 PredOp(mnem, _machInst, __opClass), 223 dest(_dest), imm(_imm), op1(_op1), 224 shiftAmt(_shiftAmt), shiftType(_shiftType) 225 {} 226 227 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 228}; 229 230#endif |